0001
0002 * Marvell ODMI for MSI support
0003
0004 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
0005 which can be used by on-board peripheral for MSI interrupts.
0006
0007 Required properties:
0008
0009 - compatible : The value here should contain:
0010
0011 "marvell,ap806-odmi-controller", "marvell,odmi-controller".
0012
0013 - interrupt,controller : Identifies the node as an interrupt controller.
0014
0015 - msi-controller : Identifies the node as an MSI controller.
0016
0017 - marvell,odmi-frames : Number of ODMI frames available. Each frame
0018 provides a number of events.
0019
0020 - reg : List of register definitions, one for each
0021 ODMI frame.
0022
0023 - marvell,spi-base : List of GIC base SPI interrupts, one for each
0024 ODMI frame. Those SPI interrupts are 0-based,
0025 i.e marvell,spi-base = <128> will use SPI #96.
0026 See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
0027 for details about the GIC Device Tree binding.
0028
0029 Example:
0030
0031 odmi: odmi@300000 {
0032 compatible = "marvell,ap806-odmi-controller",
0033 "marvell,odmi-controller";
0034 interrupt-controller;
0035 msi-controller;
0036 marvell,odmi-frames = <4>;
0037 reg = <0x300000 0x4000>,
0038 <0x304000 0x4000>,
0039 <0x308000 0x4000>,
0040 <0x30C000 0x4000>;
0041 marvell,spi-base = <128>, <136>, <144>, <152>;
0042 };
