0001 Marvell ICU Interrupt Controller
0002 --------------------------------
0003
0004 The Marvell ICU (Interrupt Consolidation Unit) controller is
0005 responsible for collecting all wired-interrupt sources in the CP and
0006 communicating them to the GIC in the AP, the unit translates interrupt
0007 requests on input wires to MSG memory mapped transactions to the GIC.
0008 These messages will access a different GIC memory area depending on
0009 their type (NSR, SR, SEI, REI, etc).
0010
0011 Required properties:
0012
0013 - compatible: Should be "marvell,cp110-icu"
0014
0015 - reg: Should contain ICU registers location and length.
0016
0017 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
0018 with their own compatible.
0019
0020 Required properties for the icu_nsr/icu_sei subnodes:
0021
0022 - compatible: Should be one of:
0023 * "marvell,cp110-icu-nsr"
0024 * "marvell,cp110-icu-sr"
0025 * "marvell,cp110-icu-sei"
0026 * "marvell,cp110-icu-rei"
0027
0028 - #interrupt-cells: Specifies the number of cells needed to encode an
0029 interrupt source. The value shall be 2.
0030
0031 The 1st cell is the index of the interrupt in the ICU unit.
0032
0033 The 2nd cell is the type of the interrupt. See arm,gic.txt for
0034 details.
0035
0036 - interrupt-controller: Identifies the node as an interrupt
0037 controller.
0038
0039 - msi-parent: Should point to the GICP controller, the GIC extension
0040 that allows to trigger interrupts using MSG memory mapped
0041 transactions.
0042
0043 Note: each 'interrupts' property referring to any 'icu_xxx' node shall
0044 have a different number within [0:206].
0045
0046 Example:
0047
0048 icu: interrupt-controller@1e0000 {
0049 compatible = "marvell,cp110-icu";
0050 reg = <0x1e0000 0x440>;
0051
0052 CP110_LABEL(icu_nsr): interrupt-controller@10 {
0053 compatible = "marvell,cp110-icu-nsr";
0054 reg = <0x10 0x20>;
0055 #interrupt-cells = <2>;
0056 interrupt-controller;
0057 msi-parent = <&gicp>;
0058 };
0059
0060 CP110_LABEL(icu_sei): interrupt-controller@50 {
0061 compatible = "marvell,cp110-icu-sei";
0062 reg = <0x50 0x10>;
0063 #interrupt-cells = <2>;
0064 interrupt-controller;
0065 msi-parent = <&sei>;
0066 };
0067 };
0068
0069 node1 {
0070 interrupt-parent = <&icu_nsr>;
0071 interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
0072 };
0073
0074 node2 {
0075 interrupt-parent = <&icu_sei>;
0076 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
0077 };
0078
0079 /* Would not work with the above nodes */
0080 node3 {
0081 interrupt-parent = <&icu_nsr>;
0082 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
0083 };
0084
0085 The legacy bindings were different in this way:
0086
0087 - #interrupt-cells: The value was 3.
0088 The 1st cell was the group type of the ICU interrupt. Possible
0089 group types were:
0090 ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
0091 ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure
0092 ICU_GRP_SEI (0x4) : System error interrupt
0093 ICU_GRP_REI (0x5) : RAM error interrupt
0094 The 2nd cell was the index of the interrupt in the ICU unit.
0095 The 3rd cell was the type of the interrupt. See arm,gic.txt for
0096 details.
0097
0098 Example:
0099
0100 icu: interrupt-controller@1e0000 {
0101 compatible = "marvell,cp110-icu";
0102 reg = <0x1e0000 0x440>;
0103
0104 #interrupt-cells = <3>;
0105 interrupt-controller;
0106 msi-parent = <&gicp>;
0107 };
0108
0109 node1 {
0110 interrupt-parent = <&icu>;
0111 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
0112 };
