0001 * ImgTec Powerdown Controller (PDC) Interrupt Controller Binding
0002
0003 This binding specifies what properties must be available in the device tree
0004 representation of a PDC IRQ controller. This has a number of input interrupt
0005 lines which can wake the system, and are passed on through output interrupt
0006 lines.
0007
0008 Required properties:
0009
0010 - compatible: Specifies the compatibility list for the interrupt controller.
0011 The type shall be <string> and the value shall include "img,pdc-intc".
0012
0013 - reg: Specifies the base PDC physical address(s) and size(s) of the
0014 addressable register space. The type shall be <prop-encoded-array>.
0015
0016 - interrupt-controller: The presence of this property identifies the node
0017 as an interrupt controller. No property value shall be defined.
0018
0019 - #interrupt-cells: Specifies the number of cells needed to encode an
0020 interrupt source. The type shall be a <u32> and the value shall be 2.
0021
0022 - num-perips: Number of waking peripherals.
0023
0024 - num-syswakes: Number of SysWake inputs.
0025
0026 - interrupts: List of interrupt specifiers. The first specifier shall be the
0027 shared SysWake interrupt, and remaining specifies shall be PDC peripheral
0028 interrupts in order.
0029
0030 * Interrupt Specifier Definition
0031
0032 Interrupt specifiers consists of 2 cells encoded as follows:
0033
0034 - <1st-cell>: The interrupt-number that identifies the interrupt source.
0035 0-7: Peripheral interrupts
0036 8-15: SysWake interrupts
0037
0038 - <2nd-cell>: The level-sense information, encoded using the Linux interrupt
0039 flags as follows (only 4 valid for peripheral interrupts):
0040 0 = none (decided by software)
0041 1 = low-to-high edge triggered
0042 2 = high-to-low edge triggered
0043 3 = both edge triggered
0044 4 = active-high level-sensitive (required for perip irqs)
0045 8 = active-low level-sensitive
0046
0047 * Examples
0048
0049 Example 1:
0050
0051 /*
0052 * TZ1090 PDC block
0053 */
0054 pdc: pdc@02006000 {
0055 // This is an interrupt controller node.
0056 interrupt-controller;
0057
0058 // Three cells to encode interrupt sources.
0059 #interrupt-cells = <2>;
0060
0061 // Offset address of 0x02006000 and size of 0x1000.
0062 reg = <0x02006000 0x1000>;
0063
0064 // Compatible with Meta hardware trigger block.
0065 compatible = "img,pdc-intc";
0066
0067 // Three peripherals are connected.
0068 num-perips = <3>;
0069
0070 // Four SysWakes are connected.
0071 num-syswakes = <4>;
0072
0073 interrupts = <18 4 /* level */>, /* Syswakes */
0074 <30 4 /* level */>, /* Peripheral 0 (RTC) */
0075 <29 4 /* level */>, /* Peripheral 1 (IR) */
0076 <31 4 /* level */>; /* Peripheral 2 (WDT) */
0077 };
0078
0079 Example 2:
0080
0081 /*
0082 * An SoC peripheral that is wired through the PDC.
0083 */
0084 rtc0 {
0085 // The interrupt controller that this device is wired to.
0086 interrupt-parent = <&pdc>;
0087
0088 // Interrupt source Peripheral 0
0089 interrupts = <0 /* Peripheral 0 (RTC) */
0090 4> /* IRQ_TYPE_LEVEL_HIGH */
0091 };
0092
0093 Example 3:
0094
0095 /*
0096 * An interrupt generating device that is wired to a SysWake pin.
0097 */
0098 touchscreen0 {
0099 // The interrupt controller that this device is wired to.
0100 interrupt-parent = <&pdc>;
0101
0102 // Interrupt source SysWake 0 that is active-low level-sensitive
0103 interrupts = <8 /* SysWake0 */
0104 8 /* IRQ_TYPE_LEVEL_LOW */>;
0105 };
