0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Freescale IRQSTEER Interrupt Multiplexer
0008
0009 maintainers:
0010 - Lucas Stach <l.stach@pengutronix.de>
0011
0012 properties:
0013 compatible:
0014 oneOf:
0015 - const: fsl,imx-irqsteer
0016 - items:
0017 - const: fsl,imx8m-irqsteer
0018 - const: fsl,imx-irqsteer
0019
0020 reg:
0021 maxItems: 1
0022
0023 interrupts:
0024 description: |
0025 should contain the up to 8 parent interrupt lines used to multiplex
0026 the input interrupts. They should be specified sequentially from
0027 output 0 to 7.
0028 items:
0029 - description: output interrupt 0
0030 - description: output interrupt 1
0031 - description: output interrupt 2
0032 - description: output interrupt 3
0033 - description: output interrupt 4
0034 - description: output interrupt 5
0035 - description: output interrupt 6
0036 - description: output interrupt 7
0037 minItems: 1
0038
0039 clocks:
0040 maxItems: 1
0041
0042 clock-names:
0043 const: ipg
0044
0045 interrupt-controller: true
0046
0047 "#interrupt-cells":
0048 const: 1
0049
0050 fsl,channel:
0051 $ref: '/schemas/types.yaml#/definitions/uint32'
0052 description: |
0053 u32 value representing the output channel that all input IRQs should be
0054 steered into.
0055
0056 fsl,num-irqs:
0057 $ref: '/schemas/types.yaml#/definitions/uint32'
0058 description: |
0059 u32 value representing the number of input interrupts of this channel,
0060 should be multiple of 32 input interrupts and up to 512 interrupts.
0061
0062 required:
0063 - compatible
0064 - reg
0065 - interrupts
0066 - clocks
0067 - clock-names
0068 - interrupt-controller
0069 - "#interrupt-cells"
0070 - fsl,channel
0071 - fsl,num-irqs
0072
0073 additionalProperties: false
0074
0075 examples:
0076 - |
0077 #include <dt-bindings/clock/imx8mq-clock.h>
0078 #include <dt-bindings/interrupt-controller/arm-gic.h>
0079
0080 interrupt-controller@32e2d000 {
0081 compatible = "fsl,imx-irqsteer";
0082 reg = <0x32e2d000 0x1000>;
0083 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0084 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
0085 clock-names = "ipg";
0086 fsl,channel = <0>;
0087 fsl,num-irqs = <64>;
0088 interrupt-controller;
0089 #interrupt-cells = <1>;
0090 };
