0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
0008
0009 maintainers:
0010 - Florian Fainelli <f.fainelli@gmail.com>
0011
0012 description: >
0013 This interrupt controller hardware is a second level interrupt controller that
0014 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
0015 platforms. It can be found on BCM7xxx products starting with BCM7120.
0016
0017 Such an interrupt controller has the following hardware design:
0018
0019 - outputs multiple interrupts signals towards its interrupt controller parent
0020
0021 - controls how some of the interrupts will be flowing, whether they will
0022 directly output an interrupt signal towards the interrupt controller parent,
0023 or if they will output an interrupt signal at this 2nd level interrupt
0024 controller, in particular for UARTs
0025
0026 - has one 32-bit enable word and one 32-bit status word
0027
0028 - no atomic set/clear operations
0029
0030 - not all bits within the interrupt controller actually map to an interrupt
0031
0032 The typical hardware layout for this controller is represented below:
0033
0034 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
0035
0036 0 -----[ MUX ] ------------|==========> GIC interrupt 75
0037 \-----------\
0038 |
0039 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
0040 \------------|
0041 |
0042 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
0043 \------------|
0044 |
0045 3 ---------------------|
0046 4 ---------------------|
0047 5 ---------------------|
0048 7 ---------------------|---|===========> GIC interrupt 66
0049 9 ---------------------|
0050 10 --------------------|
0051 11 --------------------/
0052
0053 6 ------------------------\
0054 |===========> GIC interrupt 64
0055 8 ------------------------/
0056
0057 12 ........................ X
0058 13 ........................ X (not connected)
0059 ..
0060 31 ........................ X
0061
0062 The BCM3380 Level 1 / Level 2 interrrupt controller shows up in various forms
0063 on many BCM338x/BCM63xx chipsets. It has the following properties:
0064
0065 - outputs a single interrupt signal to its interrupt controller parent
0066
0067 - contains one or more enable/status word pairs, which often appear at
0068 different offsets in different blocks
0069
0070 - no atomic set/clear operations
0071
0072 allOf:
0073 - $ref: /schemas/interrupt-controller.yaml#
0074
0075 properties:
0076 compatible:
0077 items:
0078 - enum:
0079 - brcm,bcm7120-l2-intc
0080 - brcm,bcm3380-l2-intc
0081
0082 reg:
0083 minItems: 1
0084 maxItems: 4
0085 description: >
0086 Specifies the base physical address and size of the registers
0087
0088 interrupt-controller: true
0089
0090 "#interrupt-cells":
0091 const: 1
0092
0093 interrupts:
0094 minItems: 1
0095 maxItems: 32
0096
0097 brcm,int-map-mask:
0098 $ref: /schemas/types.yaml#/definitions/uint32-array
0099 description: >
0100 32-bits bit mask describing how many and which interrupts are wired to
0101 this 2nd level interrupt controller, and how they match their respective
0102 interrupt parents. Should match exactly the number of interrupts
0103 specified in the 'interrupts' property.
0104
0105 brcm,irq-can-wake:
0106 type: boolean
0107 description: >
0108 If present, this means the L2 controller can be used as a wakeup source
0109 for system suspend/resume.
0110
0111 brcm,int-fwd-mask:
0112 $ref: /schemas/types.yaml#/definitions/uint32
0113 description: >
0114 if present, a bit mask to configure the interrupts which have a mux gate,
0115 typically UARTs. Setting these bits will make their respective interrupt
0116 outputs bypass this 2nd level interrupt controller completely; it is
0117 completely transparent for the interrupt controller parent. This should
0118 have one 32-bit word per enable/status pair.
0119
0120 additionalProperties: false
0121
0122 required:
0123 - compatible
0124 - reg
0125 - interrupt-controller
0126 - "#interrupt-cells"
0127 - interrupts
0128
0129 examples:
0130 - |
0131 irq0_intc: interrupt-controller@f0406800 {
0132 compatible = "brcm,bcm7120-l2-intc";
0133 interrupt-parent = <&intc>;
0134 #interrupt-cells = <1>;
0135 reg = <0xf0406800 0x8>;
0136 interrupt-controller;
0137 interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
0138 brcm,int-map-mask = <0xeb8>, <0x140>;
0139 brcm,int-fwd-mask = <0x7>;
0140 };
0141
0142 - |
0143 irq1_intc: interrupt-controller@10000020 {
0144 compatible = "brcm,bcm3380-l2-intc";
0145 reg = <0x10000024 0x4>, <0x1000002c 0x4>,
0146 <0x10000020 0x4>, <0x10000028 0x4>;
0147 interrupt-controller;
0148 #interrupt-cells = <1>;
0149 interrupt-parent = <&cpu_intc>;
0150 interrupts = <2>;
0151 };
