0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Broadcom BCM7038-style Level 1 interrupt controller
0008
0009 description: >
0010 This block is a first level interrupt controller that is typically connected
0011 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
0012 since BCM7038 has contained this hardware.
0013
0014 Key elements of the hardware design include:
0015
0016 - 64, 96, 128, or 160 incoming level IRQ lines
0017
0018 - Most onchip peripherals are wired directly to an L1 input
0019
0020 - A separate instance of the register set for each CPU, allowing individual
0021 peripheral IRQs to be routed to any CPU
0022
0023 - Atomic mask/unmask operations
0024
0025 - No polarity/level/edge settings
0026
0027 - No FIFO or priority encoder logic; software is expected to read all
0028 2-5 status words to determine which IRQs are pending
0029
0030 If multiple reg ranges and interrupt-parent entries are present on an SMP
0031 system, the driver will allow IRQ SMP affinity to be set up through the
0032 /proc/irq/ interface. In the simplest possible configuration, only one
0033 reg range and one interrupt-parent is needed.
0034
0035 maintainers:
0036 - Florian Fainelli <f.fainelli@gmail.com>
0037
0038 allOf:
0039 - $ref: /schemas/interrupt-controller.yaml#
0040
0041 properties:
0042 compatible:
0043 const: brcm,bcm7038-l1-intc
0044
0045 reg:
0046 description: >
0047 Specifies the base physical address and size of the registers
0048 the number of supported IRQs is inferred from the size argument
0049
0050 interrupt-controller: true
0051
0052 "#interrupt-cells":
0053 const: 1
0054
0055 interrupts:
0056 description: >
0057 Specifies the interrupt line(s) in the interrupt-parent controller node;
0058 valid values depend on the type of parent interrupt controller
0059
0060 brcm,irq-can-wake:
0061 type: boolean
0062 description: >
0063 If present, this means the L1 controller can be used as a
0064 wakeup source for system suspend/resume.
0065
0066 brcm,int-fwd-mask:
0067 $ref: /schemas/types.yaml#/definitions/uint32-array
0068 description:
0069 If present, a bit mask to indicate which interrupts have already been
0070 configured by the firmware and should be left unmanaged. This should
0071 have one 32-bit word per status/set/clear/mask group.
0072
0073 required:
0074 - compatible
0075 - reg
0076 - interrupt-controller
0077 - "#interrupt-cells"
0078 - interrupts
0079
0080 additionalProperties: false
0081
0082 examples:
0083 - |
0084 periph_intc: interrupt-controller@1041a400 {
0085 compatible = "brcm,bcm7038-l1-intc";
0086 reg = <0x1041a400 0x30>, <0x1041a600 0x30>;
0087 interrupt-controller;
0088 #interrupt-cells = <1>;
0089 interrupt-parent = <&cpu_intc>;
0090 interrupts = <2>, <3>;
0091 };
