0001 Broadcom BCM6345-style Level 1 interrupt controller
0002
0003 This block is a first level interrupt controller that is typically connected
0004 directly to one of the HW INT lines on each CPU.
0005
0006 Key elements of the hardware design include:
0007
0008 - 32, 64 or 128 incoming level IRQ lines
0009
0010 - Most onchip peripherals are wired directly to an L1 input
0011
0012 - A separate instance of the register set for each CPU, allowing individual
0013 peripheral IRQs to be routed to any CPU
0014
0015 - Contains one or more enable/status word pairs per CPU
0016
0017 - No atomic set/clear operations
0018
0019 - No polarity/level/edge settings
0020
0021 - No FIFO or priority encoder logic; software is expected to read all
0022 2-4 status words to determine which IRQs are pending
0023
0024 Required properties:
0025
0026 - compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc"
0027 - reg: specifies the base physical address and size of the registers;
0028 the number of supported IRQs is inferred from the size argument
0029 - interrupt-controller: identifies the node as an interrupt controller
0030 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
0031 source, should be 1.
0032 - interrupts: specifies the interrupt line(s) in the interrupt-parent controller
0033 node; valid values depend on the type of parent interrupt controller
0034
0035 If multiple reg ranges and interrupt-parent entries are present on an SMP
0036 system, the driver will allow IRQ SMP affinity to be set up through the
0037 /proc/irq/ interface. In the simplest possible configuration, only one
0038 reg range and one interrupt-parent is needed.
0039
0040 The driver operates in native CPU endian by default, there is no support for
0041 specifying an alternative endianness.
0042
0043 Example:
0044
0045 periph_intc: interrupt-controller@10000000 {
0046 compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc";
0047 reg = <0x10000020 0x20>,
0048 <0x10000040 0x20>;
0049
0050 interrupt-controller;
0051 #interrupt-cells = <1>;
0052
0053 interrupt-parent = <&cpu_intc>;
0054 interrupts = <2>, <3>;
0055 };
