bindings/interrupt-controller/brcm%2Cbcm2836-l1-intc.txt

0001 BCM2836 per-CPU interrupt controller
0002
0003 The BCM2836 has a per-cpu interrupt controller for the timer, PMU
0004 events, and SMP IPIs.  One of the CPUs may receive interrupts for the
0005 peripheral (GPU) events, which chain to the BCM2835-style interrupt
0006 controller.
0007
0008 Required properties:
0009
0010 - compatible:           Should be "brcm,bcm2836-l1-intc"
0011 - reg:                  Specifies base physical address and size of the
0012                           registers
0013 - interrupt-controller: Identifies the node as an interrupt controller
0014 - #interrupt-cells:     Specifies the number of cells needed to encode an
0015                           interrupt source. The value shall be 2
0016
0017 Please refer to interrupts.txt in this directory for details of the common
0018 Interrupt Controllers bindings used by client devices.
0019
0020 The interrupt sources are as follows:
0021
0022 0: CNTPSIRQ
0023 1: CNTPNSIRQ
0024 2: CNTHPIRQ
0025 3: CNTVIRQ
0026 8: GPU_FAST
0027 9: PMU_FAST
0028
0029 Example:
0030
0031 local_intc: local_intc {
0032         compatible = "brcm,bcm2836-l1-intc";
0033         reg = <0x40000000 0x100>;
0034         interrupt-controller;
0035         #interrupt-cells = <2>;
0036         interrupt-parent = <&local_intc>;
0037 };