0001 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
0002
0003 The BCM2835 contains a custom top-level interrupt controller, which supports
0004 72 interrupt sources using a 2-level register scheme. The interrupt
0005 controller, or the HW block containing it, is referred to occasionally
0006 as "armctrl" in the SoC documentation, hence naming of this binding.
0007
0008 The BCM2836 contains the same interrupt controller with the same
0009 interrupts, but the per-CPU interrupt controller is the root, and an
0010 interrupt there indicates that the ARMCTRL has an interrupt to handle.
0011
0012 Required properties:
0013
0014 - compatible : should be "brcm,bcm2835-armctrl-ic" or
0015 "brcm,bcm2836-armctrl-ic"
0016 - reg : Specifies base physical address and size of the registers.
0017 - interrupt-controller : Identifies the node as an interrupt controller
0018 - #interrupt-cells : Specifies the number of cells needed to encode an
0019 interrupt source. The value shall be 2.
0020
0021 The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
0022 pending" register, or 1/2 respectively for interrupts in the "IRQ pending
0023 1/2" register.
0024
0025 The 2nd cell contains the interrupt number within the bank. Valid values
0026 are 0..7 for bank 0, and 0..31 for bank 1.
0027
0028 Additional required properties for brcm,bcm2836-armctrl-ic:
0029 - interrupts : Specifies the interrupt on the parent for this interrupt
0030 controller to handle.
0031
0032 The interrupt sources are as follows:
0033
0034 Bank 0:
0035 0: ARM_TIMER
0036 1: ARM_MAILBOX
0037 2: ARM_DOORBELL_0
0038 3: ARM_DOORBELL_1
0039 4: VPU0_HALTED
0040 5: VPU1_HALTED
0041 6: ILLEGAL_TYPE0
0042 7: ILLEGAL_TYPE1
0043
0044 Bank 1:
0045 0: TIMER0
0046 1: TIMER1
0047 2: TIMER2
0048 3: TIMER3
0049 4: CODEC0
0050 5: CODEC1
0051 6: CODEC2
0052 7: VC_JPEG
0053 8: ISP
0054 9: VC_USB
0055 10: VC_3D
0056 11: TRANSPOSER
0057 12: MULTICORESYNC0
0058 13: MULTICORESYNC1
0059 14: MULTICORESYNC2
0060 15: MULTICORESYNC3
0061 16: DMA0
0062 17: DMA1
0063 18: VC_DMA2
0064 19: VC_DMA3
0065 20: DMA4
0066 21: DMA5
0067 22: DMA6
0068 23: DMA7
0069 24: DMA8
0070 25: DMA9
0071 26: DMA10
0072 27: DMA11-14 - shared interrupt for DMA 11 to 14
0073 28: DMAALL - triggers on all dma interrupts (including chanel 15)
0074 29: AUX
0075 30: ARM
0076 31: VPUDMA
0077
0078 Bank 2:
0079 0: HOSTPORT
0080 1: VIDEOSCALER
0081 2: CCP2TX
0082 3: SDC
0083 4: DSI0
0084 5: AVE
0085 6: CAM0
0086 7: CAM1
0087 8: HDMI0
0088 9: HDMI1
0089 10: PIXELVALVE1
0090 11: I2CSPISLV
0091 12: DSI1
0092 13: PWA0
0093 14: PWA1
0094 15: CPR
0095 16: SMI
0096 17: GPIO0
0097 18: GPIO1
0098 19: GPIO2
0099 20: GPIO3
0100 21: VC_I2C
0101 22: VC_SPI
0102 23: VC_I2SPCM
0103 24: VC_SDIO
0104 25: VC_UART
0105 26: SLIMBUS
0106 27: VEC
0107 28: CPG
0108 29: RNG
0109 30: VC_ARASANSDIO
0110 31: AVSPMON
0111
0112 Example:
0113
0114 /* BCM2835, first level */
0115 intc: interrupt-controller {
0116 compatible = "brcm,bcm2835-armctrl-ic";
0117 reg = <0x7e00b200 0x200>;
0118 interrupt-controller;
0119 #interrupt-cells = <2>;
0120 };
0121
0122 /* BCM2836, second level */
0123 intc: interrupt-controller {
0124 compatible = "brcm,bcm2836-armctrl-ic";
0125 reg = <0x7e00b200 0x200>;
0126 interrupt-controller;
0127 #interrupt-cells = <2>;
0128
0129 interrupt-parent = <&local_intc>;
0130 interrupts = <8>;
0131 };
