0001 * ARM Versatile FPGA interrupt controller
0002
0003 One or more FPGA IRQ controllers can be synthesized in an ARM reference board
0004 such as the Integrator or Versatile family. The output of these different
0005 controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
0006 instance can handle up to 32 interrupts.
0007
0008 Required properties:
0009 - compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq"
0010 - interrupt-controller: Identifies the node as an interrupt controller
0011 - #interrupt-cells: The number of cells to define the interrupts. Must be 1
0012 as the FPGA IRQ controller has no configuration options for interrupt
0013 sources. The cell is a u32 and defines the interrupt number.
0014 - reg: The register bank for the FPGA interrupt controller.
0015 - clear-mask: a u32 number representing the mask written to clear all IRQs
0016 on the controller at boot for example.
0017 - valid-mask: a u32 number representing a bit mask determining which of
0018 the interrupts are valid. Unconnected/unused lines are set to 0, and
0019 the system till not make it possible for devices to request these
0020 interrupts.
0021
0022 Example:
0023
0024 pic: pic@14000000 {
0025 compatible = "arm,versatile-fpga-irq";
0026 #interrupt-cells = <1>;
0027 interrupt-controller;
0028 reg = <0x14000000 0x100>;
0029 clear-mask = <0xffffffff>;
0030 valid-mask = <0x003fffff>;
0031 };
0032
0033 Optional properties:
0034 - interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
0035 output is simply connected to the input of another IRQ controller,
0036 then the parent IRQ shall be specified in this property.
