0001 * ARM Nested Vector Interrupt Controller (NVIC)
0002
0003 The NVIC provides an interrupt controller that is tightly coupled to
0004 Cortex-M based processor cores. The NVIC implemented on different SoCs
0005 vary in the number of interrupts and priority bits per interrupt.
0006
0007 Main node required properties:
0008
0009 - compatible : should be one of:
0010 "arm,v6m-nvic"
0011 "arm,v7m-nvic"
0012 "arm,v8m-nvic"
0013 - interrupt-controller : Identifies the node as an interrupt controller
0014 - #interrupt-cells : Specifies the number of cells needed to encode an
0015 interrupt source. The type shall be a <u32> and the value shall be 2.
0016
0017 The 1st cell contains the interrupt number for the interrupt type.
0018
0019 The 2nd cell is the priority of the interrupt.
0020
0021 - reg : Specifies base physical address(s) and size of the NVIC registers.
0022 This is at a fixed address (0xe000e100) and size (0xc00).
0023
0024 - arm,num-irq-priority-bits: The number of priority bits implemented by the
0025 given SoC
0026
0027 Example:
0028
0029 intc: interrupt-controller@e000e100 {
0030 compatible = "arm,v7m-nvic";
0031 #interrupt-cells = <2>;
0032 #address-cells = <1>;
0033 interrupt-controller;
0034 reg = <0xe000e100 0xc00>;
0035 arm,num-irq-priority-bits = <4>;
0036 };
