0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: ARM Generic Interrupt Controller v1 and v2
0008
0009 maintainers:
0010 - Marc Zyngier <marc.zyngier@arm.com>
0011
0012 description: |+
0013 ARM SMP cores are often associated with a GIC, providing per processor
0014 interrupts (PPI), shared processor interrupts (SPI) and software
0015 generated interrupts (SGI).
0016
0017 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
0018 Secondary GICs are cascaded into the upward interrupt controller and do not
0019 have PPIs or SGIs.
0020
0021 allOf:
0022 - $ref: /schemas/interrupt-controller.yaml#
0023
0024 properties:
0025 compatible:
0026 oneOf:
0027 - items:
0028 - enum:
0029 - arm,arm11mp-gic
0030 - arm,cortex-a15-gic
0031 - arm,cortex-a7-gic
0032 - arm,cortex-a5-gic
0033 - arm,cortex-a9-gic
0034 - arm,eb11mp-gic
0035 - arm,gic-400
0036 - arm,pl390
0037 - arm,tc11mp-gic
0038 - qcom,msm-8660-qgic
0039 - qcom,msm-qgic2
0040
0041 - items:
0042 - const: arm,gic-400
0043 - enum:
0044 - arm,cortex-a15-gic
0045 - arm,cortex-a7-gic
0046
0047 - items:
0048 - const: arm,arm1176jzf-devchip-gic
0049 - const: arm,arm11mp-gic
0050
0051 - items:
0052 - const: brcm,brahma-b15-gic
0053 - const: arm,cortex-a15-gic
0054
0055 - oneOf:
0056 - const: nvidia,tegra210-agic
0057 - items:
0058 - enum:
0059 - nvidia,tegra186-agic
0060 - nvidia,tegra194-agic
0061 - nvidia,tegra234-agic
0062 - const: nvidia,tegra210-agic
0063
0064 interrupt-controller: true
0065
0066 "#address-cells":
0067 enum: [ 0, 1 ]
0068 "#size-cells":
0069 const: 1
0070
0071 "#interrupt-cells":
0072 const: 3
0073 description: |
0074 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
0075 interrupts.
0076
0077 The 2nd cell contains the interrupt number for the interrupt type.
0078 SPI interrupts are in the range [0-987]. PPI interrupts are in the
0079 range [0-15].
0080
0081 The 3rd cell is the flags, encoded as follows:
0082 bits[3:0] trigger type and level flags.
0083 1 = low-to-high edge triggered
0084 2 = high-to-low edge triggered (invalid for SPIs)
0085 4 = active high level-sensitive
0086 8 = active low level-sensitive (invalid for SPIs).
0087 bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
0088 the 8 possible cpus attached to the GIC. A bit set to '1' indicated
0089 the interrupt is wired to that CPU. Only valid for PPI interrupts.
0090 Also note that the configurability of PPI interrupts is IMPLEMENTATION
0091 DEFINED and as such not guaranteed to be present (most SoC available
0092 in 2014 seem to ignore the setting of this flag and use the hardware
0093 default value).
0094
0095 reg:
0096 description: |
0097 Specifies base physical address(s) and size of the GIC registers. The
0098 first region is the GIC distributor register base and size. The 2nd region
0099 is the GIC cpu interface register base and size.
0100
0101 For GICv2 with virtualization extensions, additional regions are
0102 required for specifying the base physical address and size of the VGIC
0103 registers. The first additional region is the GIC virtual interface
0104 control register base and size. The 2nd additional region is the GIC
0105 virtual cpu interface register base and size.
0106 minItems: 2
0107 maxItems: 4
0108
0109 ranges: true
0110
0111 interrupts:
0112 description: Interrupt source of the parent interrupt controller on
0113 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
0114 below).
0115 maxItems: 1
0116
0117 cpu-offset:
0118 description: per-cpu offset within the distributor and cpu interface
0119 regions, used when the GIC doesn't have banked registers. The offset
0120 is cpu-offset * cpu-nr.
0121 $ref: /schemas/types.yaml#/definitions/uint32
0122
0123 clocks:
0124 minItems: 1
0125 maxItems: 2
0126
0127 clock-names:
0128 description: List of names for the GIC clock input(s). Valid clock names
0129 depend on the GIC variant.
0130 oneOf:
0131 - const: ic_clk # for "arm,arm11mp-gic"
0132 - const: PERIPHCLKEN # for "arm,cortex-a15-gic"
0133 - items: # for "arm,cortex-a9-gic"
0134 - const: PERIPHCLK
0135 - const: PERIPHCLKEN
0136 - const: clk # for "arm,gic-400" and "nvidia,tegra210"
0137 - const: gclk #for "arm,pl390"
0138
0139 power-domains:
0140 maxItems: 1
0141
0142 resets:
0143 maxItems: 1
0144
0145 required:
0146 - compatible
0147 - reg
0148
0149 patternProperties:
0150 "^v2m@[0-9a-f]+$":
0151 type: object
0152 description: |
0153 * GICv2m extension for MSI/MSI-x support (Optional)
0154
0155 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
0156 This is enabled by specifying v2m sub-node(s).
0157
0158 properties:
0159 compatible:
0160 const: arm,gic-v2m-frame
0161
0162 msi-controller: true
0163
0164 reg:
0165 maxItems: 1
0166 description: GICv2m MSI interface register base and size
0167
0168 arm,msi-base-spi:
0169 description: When the MSI_TYPER register contains an incorrect value,
0170 this property should contain the SPI base of the MSI frame, overriding
0171 the HW value.
0172 $ref: /schemas/types.yaml#/definitions/uint32
0173
0174 arm,msi-num-spis:
0175 description: When the MSI_TYPER register contains an incorrect value,
0176 this property should contain the number of SPIs assigned to the
0177 frame, overriding the HW value.
0178 $ref: /schemas/types.yaml#/definitions/uint32
0179
0180 required:
0181 - compatible
0182 - msi-controller
0183 - reg
0184
0185 additionalProperties: false
0186
0187 additionalProperties: false
0188
0189 examples:
0190 - |
0191 // GICv1
0192 intc: interrupt-controller@fff11000 {
0193 compatible = "arm,cortex-a9-gic";
0194 #interrupt-cells = <3>;
0195 #address-cells = <1>;
0196 interrupt-controller;
0197 reg = <0xfff11000 0x1000>,
0198 <0xfff10100 0x100>;
0199 };
0200
0201 - |
0202 // GICv2
0203 interrupt-controller@2c001000 {
0204 compatible = "arm,cortex-a15-gic";
0205 #interrupt-cells = <3>;
0206 interrupt-controller;
0207 reg = <0x2c001000 0x1000>,
0208 <0x2c002000 0x2000>,
0209 <0x2c004000 0x2000>,
0210 <0x2c006000 0x2000>;
0211 interrupts = <1 9 0xf04>;
0212 };
0213
0214 - |
0215 // GICv2m extension for MSI/MSI-x support
0216 interrupt-controller@e1101000 {
0217 compatible = "arm,gic-400";
0218 #interrupt-cells = <3>;
0219 #address-cells = <1>;
0220 #size-cells = <1>;
0221 interrupt-controller;
0222 interrupts = <1 8 0xf04>;
0223 ranges = <0 0xe1100000 0x100000>;
0224 reg = <0xe1110000 0x01000>,
0225 <0xe112f000 0x02000>,
0226 <0xe1140000 0x10000>,
0227 <0xe1160000 0x10000>;
0228
0229 v2m0: v2m@80000 {
0230 compatible = "arm,gic-v2m-frame";
0231 msi-controller;
0232 reg = <0x80000 0x1000>;
0233 };
0234
0235 //...
0236
0237 v2mN: v2m@90000 {
0238 compatible = "arm,gic-v2m-frame";
0239 msi-controller;
0240 reg = <0x90000 0x1000>;
0241 };
0242 };
0243 ...
