0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: ARM Generic Interrupt Controller, version 3
0008
0009 maintainers:
0010 - Marc Zyngier <maz@kernel.org>
0011
0012 description: |
0013 AArch64 SMP cores are often associated with a GICv3, providing Private
0014 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
0015 Software Generated Interrupts (SGI), and Locality-specific Peripheral
0016 Interrupts (LPI).
0017
0018 allOf:
0019 - $ref: /schemas/interrupt-controller.yaml#
0020
0021 properties:
0022 compatible:
0023 oneOf:
0024 - items:
0025 - enum:
0026 - qcom,msm8996-gic-v3
0027 - const: arm,gic-v3
0028 - const: arm,gic-v3
0029
0030 interrupt-controller: true
0031
0032 "#address-cells":
0033 enum: [ 0, 1, 2 ]
0034 "#size-cells":
0035 enum: [ 1, 2 ]
0036
0037 ranges: true
0038
0039 "#interrupt-cells":
0040 description: |
0041 Specifies the number of cells needed to encode an interrupt source.
0042 Must be a single cell with a value of at least 3.
0043 If the system requires describing PPI affinity, then the value must
0044 be at least 4.
0045
0046 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
0047 interrupts, 2 for interrupts in the Extended SPI range, 3 for the
0048 Extended PPI range. Other values are reserved for future use.
0049
0050 The 2nd cell contains the interrupt number for the interrupt type.
0051 SPI interrupts are in the range [0-987]. PPI interrupts are in the
0052 range [0-15]. Extented SPI interrupts are in the range [0-1023].
0053 Extended PPI interrupts are in the range [0-127].
0054
0055 The 3rd cell is the flags, encoded as follows:
0056 bits[3:0] trigger type and level flags.
0057 1 = edge triggered
0058 4 = level triggered
0059
0060 The 4th cell is a phandle to a node describing a set of CPUs this
0061 interrupt is affine to. The interrupt must be a PPI, and the node
0062 pointed must be a subnode of the "ppi-partitions" subnode. For
0063 interrupt types other than PPI or PPIs that are not partitionned,
0064 this cell must be zero. See the "ppi-partitions" node description
0065 below.
0066
0067 Cells 5 and beyond are reserved for future use and must have a value
0068 of 0 if present.
0069 enum: [ 3, 4 ]
0070
0071 reg:
0072 description: |
0073 Specifies base physical address(s) and size of the GIC
0074 registers, in the following order:
0075 - GIC Distributor interface (GICD)
0076 - GIC Redistributors (GICR), one range per redistributor region
0077 - GIC CPU interface (GICC)
0078 - GIC Hypervisor interface (GICH)
0079 - GIC Virtual CPU interface (GICV)
0080
0081 GICC, GICH and GICV are optional, but must be described if the CPUs
0082 support them. Examples of such CPUs are ARM's implementations of the
0083 ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and
0084 A73 (this list is not exhaustive).
0085
0086 minItems: 2
0087 maxItems: 4096 # Should be enough?
0088
0089 interrupts:
0090 description:
0091 Interrupt source of the VGIC maintenance interrupt.
0092 maxItems: 1
0093
0094 redistributor-stride:
0095 description:
0096 If using padding pages, specifies the stride of consecutive
0097 redistributors. Must be a multiple of 64kB.
0098 $ref: /schemas/types.yaml#/definitions/uint64
0099 multipleOf: 0x10000
0100 exclusiveMinimum: 0
0101
0102 "#redistributor-regions":
0103 description:
0104 The number of independent contiguous regions occupied by the
0105 redistributors. Required if more than one such region is present.
0106 $ref: /schemas/types.yaml#/definitions/uint32
0107 maximum: 4096
0108
0109 msi-controller:
0110 description:
0111 Only present if the Message Based Interrupt functionnality is
0112 being exposed by the HW, and the mbi-ranges property present.
0113
0114 mbi-ranges:
0115 description:
0116 A list of pairs <intid span>, where "intid" is the first SPI of a range
0117 that can be used an MBI, and "span" the size of that range. Multiple
0118 ranges can be provided.
0119 $ref: /schemas/types.yaml#/definitions/uint32-matrix
0120 items:
0121 minItems: 2
0122 maxItems: 2
0123
0124 mbi-alias:
0125 description:
0126 Address property. Base address of an alias of the GICD region containing
0127 only the {SET,CLR}SPI registers to be used if isolation is required,
0128 and if supported by the HW.
0129 $ref: /schemas/types.yaml#/definitions/uint32-array
0130 items:
0131 minItems: 1
0132 maxItems: 2
0133
0134 ppi-partitions:
0135 type: object
0136 description:
0137 PPI affinity can be expressed as a single "ppi-partitions" node,
0138 containing a set of sub-nodes.
0139 patternProperties:
0140 "^interrupt-partition-[0-9]+$":
0141 type: object
0142 properties:
0143 affinity:
0144 $ref: /schemas/types.yaml#/definitions/phandle-array
0145 items:
0146 maxItems: 1
0147 description:
0148 Should be a list of phandles to CPU nodes (as described in
0149 Documentation/devicetree/bindings/arm/cpus.yaml).
0150
0151 required:
0152 - affinity
0153
0154 clocks:
0155 maxItems: 1
0156
0157 clock-names:
0158 items:
0159 - const: aclk
0160
0161 power-domains:
0162 maxItems: 1
0163
0164 resets:
0165 maxItems: 1
0166
0167 dependencies:
0168 mbi-ranges: [ msi-controller ]
0169 msi-controller: [ mbi-ranges ]
0170
0171 required:
0172 - compatible
0173 - interrupts
0174 - reg
0175
0176 patternProperties:
0177 "^gic-its@": false
0178 "^interrupt-controller@[0-9a-f]+$": false
0179 # msi-controller is preferred, but allow other names
0180 "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
0181 type: object
0182 description:
0183 GICv3 has one or more Interrupt Translation Services (ITS) that are
0184 used to route Message Signalled Interrupts (MSI) to the CPUs.
0185 properties:
0186 compatible:
0187 const: arm,gic-v3-its
0188
0189 msi-controller: true
0190
0191 "#msi-cells":
0192 description:
0193 The single msi-cell is the DeviceID of the device which will generate
0194 the MSI.
0195 const: 1
0196
0197 reg:
0198 description:
0199 Specifies the base physical address and size of the ITS registers.
0200 maxItems: 1
0201
0202 socionext,synquacer-pre-its:
0203 description:
0204 (u32, u32) tuple describing the untranslated
0205 address and size of the pre-ITS window.
0206 $ref: /schemas/types.yaml#/definitions/uint32-array
0207 items:
0208 minItems: 2
0209 maxItems: 2
0210
0211 required:
0212 - compatible
0213 - msi-controller
0214 - "#msi-cells"
0215 - reg
0216
0217 additionalProperties: false
0218
0219 additionalProperties: false
0220
0221 examples:
0222 - |
0223 gic: interrupt-controller@2cf00000 {
0224 compatible = "arm,gic-v3";
0225 #interrupt-cells = <3>;
0226 #address-cells = <1>;
0227 #size-cells = <1>;
0228 ranges;
0229 interrupt-controller;
0230 reg = <0x2f000000 0x10000>, // GICD
0231 <0x2f100000 0x200000>, // GICR
0232 <0x2c000000 0x2000>, // GICC
0233 <0x2c010000 0x2000>, // GICH
0234 <0x2c020000 0x2000>; // GICV
0235 interrupts = <1 9 4>;
0236
0237 msi-controller;
0238 mbi-ranges = <256 128>;
0239
0240 msi-controller@2c200000 {
0241 compatible = "arm,gic-v3-its";
0242 msi-controller;
0243 #msi-cells = <1>;
0244 reg = <0x2c200000 0x20000>;
0245 };
0246 };
0247
0248 - |
0249 interrupt-controller@2c010000 {
0250 compatible = "arm,gic-v3";
0251 #interrupt-cells = <4>;
0252 #address-cells = <1>;
0253 #size-cells = <1>;
0254 ranges;
0255 interrupt-controller;
0256 redistributor-stride = <0x0 0x40000>; // 256kB stride
0257 #redistributor-regions = <2>;
0258 reg = <0x2c010000 0x10000>, // GICD
0259 <0x2d000000 0x800000>, // GICR 1: CPUs 0-31
0260 <0x2e000000 0x800000>, // GICR 2: CPUs 32-63
0261 <0x2c040000 0x2000>, // GICC
0262 <0x2c060000 0x2000>, // GICH
0263 <0x2c080000 0x2000>; // GICV
0264 interrupts = <1 9 4 0>;
0265
0266 msi-controller@2c200000 {
0267 compatible = "arm,gic-v3-its";
0268 msi-controller;
0269 #msi-cells = <1>;
0270 reg = <0x2c200000 0x20000>;
0271 };
0272
0273 msi-controller@2c400000 {
0274 compatible = "arm,gic-v3-its";
0275 msi-controller;
0276 #msi-cells = <1>;
0277 reg = <0x2c400000 0x20000>;
0278 };
0279
0280 ppi-partitions {
0281 part0: interrupt-partition-0 {
0282 affinity = <&cpu0>, <&cpu2>;
0283 };
0284
0285 part1: interrupt-partition-1 {
0286 affinity = <&cpu1>, <&cpu3>;
0287 };
0288 };
0289 };
0290
0291
0292 device@0 {
0293 reg = <0 4>;
0294 interrupts = <1 1 4 &part0>;
0295 };
0296
0297 ...
