0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Apple Interrupt Controller
0008
0009 maintainers:
0010 - Hector Martin <marcan@marcan.st>
0011
0012 description: |
0013 The Apple Interrupt Controller is a simple interrupt controller present on
0014 Apple ARM SoC platforms, including various iPhone and iPad devices and the
0015 "Apple Silicon" Macs.
0016
0017 It provides the following features:
0018
0019 - Level-triggered hardware IRQs wired to SoC blocks
0020 - Single mask bit per IRQ
0021 - Per-IRQ affinity setting
0022 - Automatic masking on event delivery (auto-ack)
0023 - Software triggering (ORed with hw line)
0024 - 2 per-CPU IPIs (meant as "self" and "other", but they are interchangeable
0025 if not symmetric)
0026 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
0027 higher priority)
0028 - Automatic masking on ack
0029 - Default "this CPU" register view and explicit per-CPU views
0030
0031 This device also represents the FIQ interrupt sources on platforms using AIC,
0032 which do not go through a discrete interrupt controller.
0033
0034 allOf:
0035 - $ref: /schemas/interrupt-controller.yaml#
0036
0037 properties:
0038 compatible:
0039 items:
0040 - const: apple,t8103-aic
0041 - const: apple,aic
0042
0043 interrupt-controller: true
0044
0045 '#interrupt-cells':
0046 const: 3
0047 description: |
0048 The 1st cell contains the interrupt type:
0049 - 0: Hardware IRQ
0050 - 1: FIQ
0051
0052 The 2nd cell contains the interrupt number.
0053 - HW IRQs: interrupt number
0054 - FIQs:
0055 - 0: physical HV timer
0056 - 1: virtual HV timer
0057 - 2: physical guest timer
0058 - 3: virtual guest timer
0059 - 4: 'efficient' CPU PMU
0060 - 5: 'performance' CPU PMU
0061
0062 The 3rd cell contains the interrupt flags. This is normally
0063 IRQ_TYPE_LEVEL_HIGH (4).
0064
0065 reg:
0066 description: |
0067 Specifies base physical address and size of the AIC registers.
0068 maxItems: 1
0069
0070 power-domains:
0071 maxItems: 1
0072
0073 affinities:
0074 type: object
0075 additionalProperties: false
0076 description:
0077 FIQ affinity can be expressed as a single "affinities" node,
0078 containing a set of sub-nodes, one per FIQ with a non-default
0079 affinity.
0080 patternProperties:
0081 "^.+-affinity$":
0082 type: object
0083 additionalProperties: false
0084 properties:
0085 apple,fiq-index:
0086 description:
0087 The interrupt number specified as a FIQ, and for which
0088 the affinity is not the default.
0089 $ref: /schemas/types.yaml#/definitions/uint32
0090 maximum: 5
0091
0092 cpus:
0093 $ref: /schemas/types.yaml#/definitions/phandle-array
0094 description:
0095 Should be a list of phandles to CPU nodes (as described in
0096 Documentation/devicetree/bindings/arm/cpus.yaml).
0097
0098 required:
0099 - apple,fiq-index
0100 - cpus
0101
0102 required:
0103 - compatible
0104 - '#interrupt-cells'
0105 - interrupt-controller
0106 - reg
0107
0108 additionalProperties: false
0109
0110 examples:
0111 - |
0112 soc {
0113 #address-cells = <2>;
0114 #size-cells = <2>;
0115
0116 aic: interrupt-controller@23b100000 {
0117 compatible = "apple,t8103-aic", "apple,aic";
0118 #interrupt-cells = <3>;
0119 interrupt-controller;
0120 reg = <0x2 0x3b100000 0x0 0x8000>;
0121 };
0122 };
