0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Actions Semi Owl SoCs SIRQ interrupt controller
0008
0009 maintainers:
0010 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
0011 - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
0012
0013 description: |
0014 This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700
0015 and S900) and provides support for handling up to 3 external interrupt lines.
0016
0017 properties:
0018 compatible:
0019 enum:
0020 - actions,s500-sirq
0021 - actions,s700-sirq
0022 - actions,s900-sirq
0023
0024 reg:
0025 maxItems: 1
0026
0027 interrupt-controller: true
0028
0029 '#interrupt-cells':
0030 const: 2
0031 description:
0032 The first cell is the input IRQ number, between 0 and 2, while the second
0033 cell is the trigger type as defined in interrupt.txt in this directory.
0034
0035 'interrupts':
0036 description: |
0037 Contains the GIC SPI IRQs mapped to the external interrupt lines.
0038 They shall be specified sequentially from output 0 to 2.
0039 minItems: 3
0040 maxItems: 3
0041
0042 required:
0043 - compatible
0044 - reg
0045 - interrupt-controller
0046 - '#interrupt-cells'
0047 - 'interrupts'
0048
0049 additionalProperties: false
0050
0051 examples:
0052 - |
0053 #include <dt-bindings/interrupt-controller/arm-gic.h>
0054
0055 sirq: interrupt-controller@b01b0200 {
0056 compatible = "actions,s500-sirq";
0057 reg = <0xb01b0200 0x4>;
0058 interrupt-controller;
0059 #interrupt-cells = <2>;
0060 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
0061 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
0062 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
0063 };
0064
0065 ...
