0001 TB10x Top Level Interrupt Controller
0002 ====================================
0003
0004 The Abilis TB10x SOC contains a custom interrupt controller. It performs
0005 one-to-one mapping of external interrupt sources to CPU interrupts and
0006 provides support for reconfigurable trigger modes.
0007
0008 Required properties
0009 -------------------
0010
0011 - compatible: Should be "abilis,tb10x-ictl"
0012 - reg: specifies physical base address and size of register range.
0013 - interrupt-congroller: Identifies the node as an interrupt controller.
0014 - #interrupt cells: Specifies the number of cells used to encode an interrupt
0015 source connected to this controller. The value shall be 2.
0016 - interrupts: Specifies the list of interrupt lines which are handled by
0017 the interrupt controller in the parent controller's notation. Interrupts
0018 are mapped one-to-one to parent interrupts.
0019
0020 Example
0021 -------
0022
0023 intc: interrupt-controller { /* Parent interrupt controller */
0024 interrupt-controller;
0025 #interrupt-cells = <1>; /* For example below */
0026 /* ... */
0027 };
0028
0029 tb10x_ictl: pic@2000 { /* TB10x interrupt controller */
0030 compatible = "abilis,tb10x-ictl";
0031 reg = <0x2000 0x20>;
0032 interrupt-controller;
0033 #interrupt-cells = <2>;
0034 interrupt-parent = <&intc>;
0035 interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0036 20 21 22 23 24 25 26 27 28 29 30 31>;
0037 };
