0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
0008
0009 maintainers:
0010 - Jia-Wei Chang <jia-wei.chang@mediatek.com>
0011 - Johnson Wang <johnson.wang@mediatek.com>
0012
0013 description: |
0014 MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
0015 MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
0016 hardware. It can also optimize the voltage to reduce the power consumption.
0017
0018 properties:
0019 compatible:
0020 enum:
0021 - mediatek,mt8183-cci
0022 - mediatek,mt8186-cci
0023
0024 clocks:
0025 items:
0026 - description:
0027 The multiplexer for clock input of the bus.
0028 - description:
0029 A parent of "bus" clock which is used as an intermediate clock source
0030 when the original clock source (PLL) is under transition and not
0031 stable yet.
0032
0033 clock-names:
0034 items:
0035 - const: cci
0036 - const: intermediate
0037
0038 operating-points-v2: true
0039 opp-table: true
0040
0041 proc-supply:
0042 description:
0043 Phandle of the regulator for CCI that provides the supply voltage.
0044
0045 sram-supply:
0046 description:
0047 Phandle of the regulator for sram of CCI that provides the supply
0048 voltage. When it is present, the implementation needs to do
0049 "voltage tracking" to step by step scale up/down Vproc and Vsram to fit
0050 SoC specific needs. When absent, the voltage scaling flow is handled by
0051 hardware, hence no software "voltage tracking" is needed.
0052
0053 required:
0054 - compatible
0055 - clocks
0056 - clock-names
0057 - operating-points-v2
0058 - proc-supply
0059
0060 additionalProperties: false
0061
0062 examples:
0063 - |
0064 #include <dt-bindings/clock/mt8183-clk.h>
0065 cci: cci {
0066 compatible = "mediatek,mt8183-cci";
0067 clocks = <&mcucfg CLK_MCU_BUS_SEL>,
0068 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
0069 clock-names = "cci", "intermediate";
0070 operating-points-v2 = <&cci_opp>;
0071 proc-supply = <&mt6358_vproc12_reg>;
0072 };
0073
0074 cci_opp: opp-table-cci {
0075 compatible = "operating-points-v2";
0076 opp-shared;
0077 opp2_00: opp-273000000 {
0078 opp-hz = /bits/ 64 <273000000>;
0079 opp-microvolt = <650000>;
0080 };
0081 opp2_01: opp-338000000 {
0082 opp-hz = /bits/ 64 <338000000>;
0083 opp-microvolt = <687500>;
0084 };
0085 opp2_02: opp-403000000 {
0086 opp-hz = /bits/ 64 <403000000>;
0087 opp-microvolt = <718750>;
0088 };
0089 opp2_03: opp-463000000 {
0090 opp-hz = /bits/ 64 <463000000>;
0091 opp-microvolt = <756250>;
0092 };
0093 opp2_04: opp-546000000 {
0094 opp-hz = /bits/ 64 <546000000>;
0095 opp-microvolt = <800000>;
0096 };
0097 opp2_05: opp-624000000 {
0098 opp-hz = /bits/ 64 <624000000>;
0099 opp-microvolt = <818750>;
0100 };
0101 opp2_06: opp-689000000 {
0102 opp-hz = /bits/ 64 <689000000>;
0103 opp-microvolt = <850000>;
0104 };
0105 opp2_07: opp-767000000 {
0106 opp-hz = /bits/ 64 <767000000>;
0107 opp-microvolt = <868750>;
0108 };
0109 opp2_08: opp-845000000 {
0110 opp-hz = /bits/ 64 <845000000>;
0111 opp-microvolt = <893750>;
0112 };
0113 opp2_09: opp-871000000 {
0114 opp-hz = /bits/ 64 <871000000>;
0115 opp-microvolt = <906250>;
0116 };
0117 opp2_10: opp-923000000 {
0118 opp-hz = /bits/ 64 <923000000>;
0119 opp-microvolt = <931250>;
0120 };
0121 opp2_11: opp-962000000 {
0122 opp-hz = /bits/ 64 <962000000>;
0123 opp-microvolt = <943750>;
0124 };
0125 opp2_12: opp-1027000000 {
0126 opp-hz = /bits/ 64 <1027000000>;
0127 opp-microvolt = <975000>;
0128 };
0129 opp2_13: opp-1092000000 {
0130 opp-hz = /bits/ 64 <1092000000>;
0131 opp-microvolt = <1000000>;
0132 };
0133 opp2_14: opp-1144000000 {
0134 opp-hz = /bits/ 64 <1144000000>;
0135 opp-microvolt = <1025000>;
0136 };
0137 opp2_15: opp-1196000000 {
0138 opp-hz = /bits/ 64 <1196000000>;
0139 opp-microvolt = <1050000>;
0140 };
0141 };
