bindings/interconnect/fsl%2Cimx8m-noc.yaml

0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Generic i.MX bus frequency device
0008
0009 maintainers:
0010   - Peng Fan <peng.fan@nxp.com>
0011
0012 description: |
0013   The i.MX SoC family has multiple buses for which clock frequency (and
0014   sometimes voltage) can be adjusted.
0015
0016   Some of those buses expose register areas mentioned in the memory maps as GPV
0017   ("Global Programmers View") but not all. Access to this area might be denied
0018   for normal (non-secure) world.
0019
0020   The buses are based on externally licensed IPs such as ARM NIC-301 and
0021   Arteris FlexNOC but DT bindings are specific to the integration of these bus
0022   interconnect IPs into imx SOCs.
0023
0024 properties:
0025   compatible:
0026     oneOf:
0027       - items:
0028           - enum:
0029               - fsl,imx8mm-nic
0030               - fsl,imx8mn-nic
0031               - fsl,imx8mp-nic
0032               - fsl,imx8mq-nic
0033           - const: fsl,imx8m-nic
0034       - items:
0035           - enum:
0036               - fsl,imx8mm-noc
0037               - fsl,imx8mn-noc
0038               - fsl,imx8mp-noc
0039               - fsl,imx8mq-noc
0040           - const: fsl,imx8m-noc
0041       - const: fsl,imx8m-nic
0042
0043   reg:
0044     maxItems: 1
0045
0046   clocks:
0047     maxItems: 1
0048
0049   operating-points-v2: true
0050   opp-table: true
0051
0052   fsl,ddrc:
0053     $ref: "/schemas/types.yaml#/definitions/phandle"
0054     description:
0055       Phandle to DDR Controller.
0056
0057   '#interconnect-cells':
0058     description:
0059       If specified then also act as an interconnect provider. Should only be
0060       set once per soc on the main noc.
0061     const: 1
0062
0063 required:
0064   - compatible
0065   - clocks
0066
0067 additionalProperties: false
0068
0069 examples:
0070   - |
0071     #include <dt-bindings/clock/imx8mm-clock.h>
0072     #include <dt-bindings/interconnect/imx8mm.h>
0073     #include <dt-bindings/interrupt-controller/arm-gic.h>
0074
0075     noc: interconnect@32700000 {
0076         compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc";
0077         reg = <0x32700000 0x100000>;
0078         clocks = <&clk IMX8MM_CLK_NOC>;
0079         #interconnect-cells = <1>;
0080         fsl,ddrc = <&ddrc>;
0081
0082         operating-points-v2 = <&noc_opp_table>;
0083         noc_opp_table: opp-table {
0084             compatible = "operating-points-v2";
0085
0086             opp-133333333 {
0087                 opp-hz = /bits/ 64 <133333333>;
0088             };
0089             opp-800000000 {
0090                 opp-hz = /bits/ 64 <800000000>;
0091             };
0092         };
0093     };
0094
0095     ddrc: memory-controller@3d400000 {
0096         compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
0097         reg = <0x3d400000 0x400000>;
0098         clock-names = "core", "pll", "alt", "apb";
0099         clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
0100                  <&clk IMX8MM_DRAM_PLL>,
0101                  <&clk IMX8MM_CLK_DRAM_ALT>,
0102                  <&clk IMX8MM_CLK_DRAM_APB>;
0103     };