0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/iio/resolver/adi,ad2s90.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Analog Devices AD2S90 Resolver-to-Digital Converter
0008
0009 maintainers:
0010 - Matheus Tavares <matheus.bernardino@usp.br>
0011
0012 description: |
0013 Datasheet: https://www.analog.com/en/products/ad2s90.html
0014
0015 properties:
0016 compatible:
0017 const: adi,ad2s90
0018
0019 reg:
0020 maxItems: 1
0021
0022 spi-max-frequency:
0023 maximum: 830000
0024 description: |
0025 Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns
0026 delay is expected between the application of a logic LO to CS and the
0027 application of SCLK, as also specified. And since the delay is not
0028 implemented in the spi code, to satisfy it, SCLK's period should be at
0029 most 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives
0030 roughly 830000Hz.
0031
0032 spi-cpol: true
0033
0034 spi-cpha: true
0035
0036 additionalProperties: false
0037
0038 required:
0039 - compatible
0040 - reg
0041
0042 dependencies:
0043 spi-cpol: [ spi-cpha ]
0044 spi-cpha: [ spi-cpol ]
0045
0046 examples:
0047 - |
0048 spi {
0049 #address-cells = <1>;
0050 #size-cells = <0>;
0051
0052 resolver@0 {
0053 compatible = "adi,ad2s90";
0054 reg = <0>;
0055 spi-max-frequency = <830000>;
0056 spi-cpol;
0057 spi-cpha;
0058 };
0059 };
0060 ...
