0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/iio/imu/adi,adis16480.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Analog Devices ADIS16480 and similar IMUs
0008
0009 maintainers:
0010 - Alexandru Tachici <alexandru.tachici@analog.com>
0011
0012 properties:
0013 compatible:
0014 enum:
0015 - adi,adis16375
0016 - adi,adis16480
0017 - adi,adis16485
0018 - adi,adis16488
0019 - adi,adis16490
0020 - adi,adis16495-1
0021 - adi,adis16495-2
0022 - adi,adis16495-3
0023 - adi,adis16497-1
0024 - adi,adis16497-2
0025 - adi,adis16497-3
0026
0027 reg:
0028 maxItems: 1
0029
0030 interrupts:
0031 minItems: 1
0032 maxItems: 2
0033 description: |
0034 Accepted interrupt types are:
0035 * IRQ_TYPE_EDGE_RISING
0036 * IRQ_TYPE_EDGE_FALLING
0037
0038 interrupt-names:
0039 minItems: 1
0040 maxItems: 2
0041 description:
0042 Default if not supplied is DIO1.
0043 items:
0044 enum:
0045 - DIO1
0046 - DIO2
0047 - DIO3
0048 - DIO4
0049
0050 spi-max-frequency: true
0051
0052 spi-cpha: true
0053 spi-cpol: true
0054
0055 reset-gpios:
0056 maxItems: 1
0057 description: Connected to RESET pin which is active low.
0058
0059 clocks:
0060 maxItems: 1
0061 description: If not provided, then the internal clock is used.
0062
0063 clock-names:
0064 description: |
0065 sync: In sync mode, the internal clock is disabled and the frequency
0066 of the external clock signal establishes therate of data
0067 collection and processing. See Fig 14 and 15 in the datasheet.
0068 The clock-frequency must be:
0069 * 3000 to 4500 Hz for adis1649x devices.
0070 * 700 to 2400 Hz for adis1648x devices.
0071 pps: In Pulse Per Second (PPS) Mode, the rate of data collection and
0072 production is equal to the product of the external clock
0073 frequency and the scale factor in the SYNC_SCALE register, see
0074 Table 154 in the datasheet.
0075 The clock-frequency must be:
0076 * 1 to 128 Hz for adis1649x devices.
0077 * This mode is not supported by adis1648x devices.
0078 enum:
0079 - sync
0080 - pps
0081
0082 adi,ext-clk-pin:
0083 $ref: /schemas/types.yaml#/definitions/string
0084 description: |
0085 The DIOx line to be used as an external clock input.
0086 Each DIOx pin supports only one function at a time (data ready line
0087 selection or external clock input). When a single pin has two
0088 two assignments, the enable bit for the lower priority function
0089 automatically resets to zero (disabling the lower priority function).
0090 Data ready has highest priority.
0091 If not provided then DIO2 is assigned as default external clock
0092 input pin.
0093 enum:
0094 - DIO1
0095 - DIO2
0096 - DIO3
0097 - DIO4
0098
0099 additionalProperties: false
0100
0101 required:
0102 - compatible
0103 - reg
0104 - interrupts
0105 - spi-cpha
0106 - spi-cpol
0107 - spi-max-frequency
0108
0109 examples:
0110 - |
0111 #include <dt-bindings/interrupt-controller/irq.h>
0112 spi {
0113 #address-cells = <1>;
0114 #size-cells = <0>;
0115
0116 imu@0 {
0117 compatible = "adi,adis16495-1";
0118 reg = <0>;
0119 spi-max-frequency = <3200000>;
0120 spi-cpol;
0121 spi-cpha;
0122 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
0123 interrupt-parent = <&gpio>;
0124 interrupt-names = "DIO2";
0125 clocks = <&adis16495_sync>;
0126 clock-names = "sync";
0127 adi,ext-clk-pin = "DIO1";
0128 };
0129 };
0130 ...
