0001 Xilinx XADC device driver
0002
0003 This binding document describes the bindings for the Xilinx 7 Series XADC as well
0004 as the UltraScale/UltraScale+ System Monitor.
0005
0006 The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
0007 The XADC has a DRP interface for communication. Currently two different
0008 frontends for the DRP interface exist. One that is only available on the ZYNQ
0009 family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
0010 on all series 7 platforms and is a softmacro with a AXI interface. This binding
0011 document describes the bindings for both of them since the bindings are very
0012 similar.
0013
0014 The Xilinx System Monitor is an ADC that is found in the UltraScale and
0015 UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
0016 communication. Xilinx provides a standard IP core that can be used to access the
0017 System Monitor through an AXI interface in the FPGA fabric. This IP core is
0018 called the Xilinx System Management Wizard. This document describes the bindings
0019 for this IP.
0020
0021 Required properties:
0022 - compatible: Should be one of
0023 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
0024 configuration interface to interface to the XADC hardmacro.
0025 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
0026 interface to the XADC hardmacro.
0027 * "xlnx,system-management-wiz-1.3": When using the
0028 Xilinx System Management Wizard fabric IP core to access the
0029 UltraScale and UltraScale+ System Monitor.
0030 - reg: Address and length of the register set for the device
0031 - interrupts: Interrupt for the XADC control interface.
0032 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
0033 when using the axi-xadc or the axi-system-management-wizard this must be
0034 the clock that provides the clock to the AXI bus interface of the core.
0035
0036 Optional properties:
0037 - xlnx,external-mux:
0038 * "none": No external multiplexer is used, this is the default
0039 if the property is omitted.
0040 * "single": External multiplexer mode is used with one
0041 multiplexer.
0042 * "dual": External multiplexer mode is used with two
0043 multiplexers for simultaneous sampling.
0044 - xlnx,external-mux-channel: Configures which pair of pins is used to
0045 sample data in external mux mode.
0046 Valid values for single external multiplexer mode are:
0047 0: VP/VN
0048 1: VAUXP[0]/VAUXN[0]
0049 2: VAUXP[1]/VAUXN[1]
0050 ...
0051 16: VAUXP[15]/VAUXN[15]
0052 Valid values for dual external multiplexer mode are:
0053 1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
0054 2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
0055 ...
0056 8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
0057
0058 This property needs to be present if the device is configured for
0059 external multiplexer mode (either single or dual). If the device is
0060 not using external multiplexer mode the property is ignored.
0061 - xnlx,channels: List of external channels that are connected to the ADC
0062 Required properties:
0063 * #address-cells: Should be 1.
0064 * #size-cells: Should be 0.
0065
0066 The child nodes of this node represent the external channels which are
0067 connected to the ADC. If the property is no present no external
0068 channels will be assumed to be connected.
0069
0070 Each child node represents one channel and has the following
0071 properties:
0072 Required properties:
0073 * reg: Pair of pins the channel is connected to.
0074 0: VP/VN
0075 1: VAUXP[0]/VAUXN[0]
0076 2: VAUXP[1]/VAUXN[1]
0077 ...
0078 16: VAUXP[15]/VAUXN[15]
0079 Note each channel number should only be used at most
0080 once.
0081 Optional properties:
0082 * xlnx,bipolar: If set the channel is used in bipolar
0083 mode.
0084
0085
0086 Examples:
0087 xadc@f8007100 {
0088 compatible = "xlnx,zynq-xadc-1.00.a";
0089 reg = <0xf8007100 0x20>;
0090 interrupts = <0 7 4>;
0091 interrupt-parent = <&gic>;
0092 clocks = <&pcap_clk>;
0093
0094 xlnx,channels {
0095 #address-cells = <1>;
0096 #size-cells = <0>;
0097 channel@0 {
0098 reg = <0>;
0099 };
0100 channel@1 {
0101 reg = <1>;
0102 };
0103 channel@8 {
0104 reg = <8>;
0105 };
0106 };
0107 };
0108
0109 xadc@43200000 {
0110 compatible = "xlnx,axi-xadc-1.00.a";
0111 reg = <0x43200000 0x1000>;
0112 interrupts = <0 53 4>;
0113 interrupt-parent = <&gic>;
0114 clocks = <&fpga1_clk>;
0115
0116 xlnx,channels {
0117 #address-cells = <1>;
0118 #size-cells = <0>;
0119 channel@0 {
0120 reg = <0>;
0121 xlnx,bipolar;
0122 };
0123 };
0124 };
0125
0126 adc@80000000 {
0127 compatible = "xlnx,system-management-wiz-1.3";
0128 reg = <0x80000000 0x1000>;
0129 interrupts = <0 81 4>;
0130 interrupt-parent = <&gic>;
0131 clocks = <&fpga1_clk>;
0132
0133 xlnx,channels {
0134 #address-cells = <1>;
0135 #size-cells = <0>;
0136 channel@0 {
0137 reg = <0>;
0138 xlnx,bipolar;
0139 };
0140 };
0141 };
