0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: STMicroelectronics STM32 ADC bindings
0008
0009 description: |
0010 STM32 ADC is a successive approximation analog-to-digital converter.
0011 It has several multiplexed input channels. Conversions can be performed
0012 in single, continuous, scan or discontinuous mode. Result of the ADC is
0013 stored in a left-aligned or right-aligned 32-bit data register.
0014 Conversions can be launched in software or using hardware triggers.
0015
0016 The analog watchdog feature allows the application to detect if the input
0017 voltage goes beyond the user-defined, higher or lower thresholds.
0018
0019 Each STM32 ADC block can have up to 3 ADC instances.
0020
0021 maintainers:
0022 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
0023
0024 properties:
0025 compatible:
0026 enum:
0027 - st,stm32f4-adc-core
0028 - st,stm32h7-adc-core
0029 - st,stm32mp1-adc-core
0030
0031 reg:
0032 maxItems: 1
0033
0034 interrupts:
0035 description: |
0036 One or more interrupts for ADC block, depending on part used:
0037 - stm32f4 and stm32h7 share a common ADC interrupt line.
0038 - stm32mp1 has two separate interrupt lines, one for each ADC within
0039 ADC block.
0040 minItems: 1
0041 maxItems: 2
0042
0043 clocks:
0044 minItems: 1
0045 maxItems: 2
0046 description: |
0047 Core can use up to two clocks, depending on part used:
0048 - "adc" clock: for the analog circuitry, common to all ADCs.
0049 It's required on stm32f4.
0050 It's optional on stm32h7 and stm32mp1.
0051 - "bus" clock: for registers access, common to all ADCs.
0052 It's not present on stm32f4.
0053 It's required on stm32h7 and stm32mp1.
0054
0055 clock-names: true
0056
0057 st,max-clk-rate-hz:
0058 description:
0059 Allow to specify desired max clock rate used by analog circuitry.
0060
0061 vdda-supply:
0062 description: Phandle to the vdda input analog voltage.
0063
0064 vref-supply:
0065 description: Phandle to the vref input analog reference voltage.
0066
0067 booster-supply:
0068 description:
0069 Phandle to the embedded booster regulator that can be used to supply ADC
0070 analog input switches on stm32h7 and stm32mp1.
0071
0072 vdd-supply:
0073 description:
0074 Phandle to the vdd input voltage. It can be used to supply ADC analog
0075 input switches on stm32mp1.
0076
0077 st,syscfg:
0078 description:
0079 Phandle to system configuration controller. It can be used to control the
0080 analog circuitry on stm32mp1.
0081 $ref: "/schemas/types.yaml#/definitions/phandle-array"
0082
0083 interrupt-controller: true
0084
0085 '#interrupt-cells':
0086 const: 1
0087
0088 '#address-cells':
0089 const: 1
0090
0091 '#size-cells':
0092 const: 0
0093
0094 allOf:
0095 - if:
0096 properties:
0097 compatible:
0098 contains:
0099 const: st,stm32f4-adc-core
0100
0101 then:
0102 properties:
0103 clocks:
0104 maxItems: 1
0105
0106 clock-names:
0107 const: adc
0108
0109 interrupts:
0110 items:
0111 - description: interrupt line common for all ADCs
0112
0113 st,max-clk-rate-hz:
0114 minimum: 600000
0115 maximum: 36000000
0116 default: 36000000
0117
0118 booster-supply: false
0119
0120 vdd-supply: false
0121
0122 st,syscfg: false
0123
0124 - if:
0125 properties:
0126 compatible:
0127 contains:
0128 const: st,stm32h7-adc-core
0129
0130 then:
0131 properties:
0132 clocks:
0133 minItems: 1
0134 maxItems: 2
0135
0136 clock-names:
0137 items:
0138 - const: bus
0139 - const: adc
0140 minItems: 1
0141
0142 interrupts:
0143 items:
0144 - description: interrupt line common for all ADCs
0145
0146 st,max-clk-rate-hz:
0147 minimum: 120000
0148 maximum: 36000000
0149 default: 36000000
0150
0151 vdd-supply: false
0152
0153 st,syscfg: false
0154
0155 - if:
0156 properties:
0157 compatible:
0158 contains:
0159 const: st,stm32mp1-adc-core
0160
0161 then:
0162 properties:
0163 clocks:
0164 minItems: 1
0165 maxItems: 2
0166
0167 clock-names:
0168 items:
0169 - const: bus
0170 - const: adc
0171 minItems: 1
0172
0173 interrupts:
0174 items:
0175 - description: interrupt line for ADC1
0176 - description: interrupt line for ADC2
0177
0178 st,max-clk-rate-hz:
0179 minimum: 120000
0180 maximum: 36000000
0181 default: 36000000
0182
0183 additionalProperties: false
0184
0185 required:
0186 - compatible
0187 - reg
0188 - interrupts
0189 - clocks
0190 - clock-names
0191 - vdda-supply
0192 - vref-supply
0193 - interrupt-controller
0194 - '#interrupt-cells'
0195 - '#address-cells'
0196 - '#size-cells'
0197
0198 patternProperties:
0199 "^adc@[0-9]+$":
0200 type: object
0201 description:
0202 An ADC block node should contain at least one subnode, representing an
0203 ADC instance available on the machine.
0204
0205 properties:
0206 compatible:
0207 enum:
0208 - st,stm32f4-adc
0209 - st,stm32h7-adc
0210 - st,stm32mp1-adc
0211
0212 reg:
0213 description: |
0214 Offset of ADC instance in ADC block. Valid values are:
0215 - 0x0: ADC1
0216 - 0x100: ADC2
0217 - 0x200: ADC3 (stm32f4 only)
0218 maxItems: 1
0219
0220 '#io-channel-cells':
0221 const: 1
0222
0223 '#address-cells':
0224 const: 1
0225
0226 '#size-cells':
0227 const: 0
0228
0229 interrupts:
0230 description: |
0231 IRQ Line for the ADC instance. Valid values are:
0232 - 0 for adc@0
0233 - 1 for adc@100
0234 - 2 for adc@200 (stm32f4 only)
0235 maxItems: 1
0236
0237 clocks:
0238 description:
0239 Input clock private to this ADC instance. It's required only on
0240 stm32f4, that has per instance clock input for registers access.
0241 maxItems: 1
0242
0243 dmas:
0244 description: RX DMA Channel
0245 maxItems: 1
0246
0247 dma-names:
0248 const: rx
0249
0250 assigned-resolution-bits:
0251 description: |
0252 Resolution (bits) to use for conversions:
0253 - can be 6, 8, 10 or 12 on stm32f4
0254 - can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
0255
0256 st,adc-channels:
0257 description: |
0258 List of single-ended channels muxed for this ADC. It can have up to:
0259 - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
0260 - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
0261 stm32mp1.
0262 $ref: /schemas/types.yaml#/definitions/uint32-array
0263 deprecated: true
0264
0265 st,adc-diff-channels:
0266 description: |
0267 List of differential channels muxed for this ADC. Some channels can
0268 be configured as differential instead of single-ended on stm32h7 and
0269 on stm32mp1. Positive and negative inputs pairs are listed:
0270 <vinp vinn>, <vinp vinn>,... vinp and vinn are numbered from 0 to 19.
0271
0272 Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
0273 required if no adc generic channel is defined. These legacy channel
0274 properties are exclusive with adc generic channel bindings.
0275 Both properties can be used together. Some channels can be
0276 used as single-ended and some other ones as differential (mixed). But
0277 channels can't be configured both as single-ended and differential.
0278 $ref: /schemas/types.yaml#/definitions/uint32-matrix
0279 items:
0280 items:
0281 - description: |
0282 "vinp" indicates positive input number
0283 minimum: 0
0284 maximum: 19
0285 - description: |
0286 "vinn" indicates negative input number
0287 minimum: 0
0288 maximum: 19
0289 deprecated: true
0290
0291 st,min-sample-time-nsecs:
0292 description:
0293 Minimum sampling time in nanoseconds. Depending on hardware (board)
0294 e.g. high/low analog input source impedance, fine tune of ADC
0295 sampling time may be recommended. This can be either one value or an
0296 array that matches "st,adc-channels" and/or "st,adc-diff-channels"
0297 list, to set sample time resp. for all channels, or independently for
0298 each channel.
0299 $ref: /schemas/types.yaml#/definitions/uint32-array
0300 deprecated: true
0301
0302 nvmem-cells:
0303 items:
0304 - description: Phandle to the calibration vrefint data provided by otp
0305
0306 nvmem-cell-names:
0307 items:
0308 - const: vrefint
0309
0310 patternProperties:
0311 "^channel@([0-9]|1[0-9])$":
0312 type: object
0313 $ref: "adc.yaml"
0314 description: Represents the external channels which are connected to the ADC.
0315
0316 properties:
0317 reg:
0318 items:
0319 minimum: 0
0320 maximum: 19
0321
0322 label:
0323 description: |
0324 Unique name to identify which channel this is.
0325 Reserved label names "vddcore", "vrefint" and "vbat"
0326 are used to identify internal channels with matching names.
0327
0328 diff-channels:
0329 $ref: /schemas/types.yaml#/definitions/uint32-array
0330 items:
0331 minimum: 0
0332 maximum: 19
0333
0334 st,min-sample-time-ns:
0335 description: |
0336 Minimum sampling time in nanoseconds. Depending on hardware (board)
0337 e.g. high/low analog input source impedance, fine tune of ADC
0338 sampling time may be recommended.
0339
0340 required:
0341 - reg
0342
0343 additionalProperties: false
0344
0345 allOf:
0346 - if:
0347 properties:
0348 compatible:
0349 contains:
0350 const: st,stm32f4-adc
0351
0352 then:
0353 properties:
0354 reg:
0355 enum:
0356 - 0x0
0357 - 0x100
0358 - 0x200
0359
0360 interrupts:
0361 minimum: 0
0362 maximum: 2
0363
0364 assigned-resolution-bits:
0365 enum: [6, 8, 10, 12]
0366 default: 12
0367
0368 st,adc-channels:
0369 minItems: 1
0370 maxItems: 16
0371 items:
0372 minimum: 0
0373 maximum: 15
0374
0375 st,adc-diff-channels: false
0376
0377 st,min-sample-time-nsecs:
0378 minItems: 1
0379 maxItems: 16
0380 items:
0381 minimum: 80
0382
0383 required:
0384 - clocks
0385
0386 - if:
0387 properties:
0388 compatible:
0389 contains:
0390 enum:
0391 - st,stm32h7-adc
0392 - st,stm32mp1-adc
0393
0394 then:
0395 properties:
0396 reg:
0397 enum:
0398 - 0x0
0399 - 0x100
0400
0401 interrupts:
0402 minimum: 0
0403 maximum: 1
0404
0405 assigned-resolution-bits:
0406 enum: [8, 10, 12, 14, 16]
0407 default: 16
0408
0409 st,adc-channels:
0410 minItems: 1
0411 maxItems: 20
0412 items:
0413 minimum: 0
0414 maximum: 19
0415
0416 st,min-sample-time-nsecs:
0417 minItems: 1
0418 maxItems: 20
0419 items:
0420 minimum: 40
0421
0422 additionalProperties: false
0423
0424 required:
0425 - compatible
0426 - reg
0427 - interrupts
0428 - '#io-channel-cells'
0429
0430 examples:
0431 - |
0432 // Example 1: with stm32f429, ADC1, single-ended channel 8
0433 adc123: adc@40012000 {
0434 compatible = "st,stm32f4-adc-core";
0435 reg = <0x40012000 0x400>;
0436 interrupts = <18>;
0437 clocks = <&rcc 0 168>;
0438 clock-names = "adc";
0439 st,max-clk-rate-hz = <36000000>;
0440 vdda-supply = <&vdda>;
0441 vref-supply = <&vref>;
0442 interrupt-controller;
0443 #interrupt-cells = <1>;
0444 #address-cells = <1>;
0445 #size-cells = <0>;
0446 adc@0 {
0447 compatible = "st,stm32f4-adc";
0448 #io-channel-cells = <1>;
0449 reg = <0x0>;
0450 clocks = <&rcc 0 168>;
0451 interrupt-parent = <&adc123>;
0452 interrupts = <0>;
0453 st,adc-channels = <8>;
0454 dmas = <&dma2 0 0 0x400 0x0>;
0455 dma-names = "rx";
0456 assigned-resolution-bits = <8>;
0457 };
0458 // ...
0459 // other adc child nodes follow...
0460 };
0461
0462 - |
0463 // Example 2: with stm32mp157c to setup ADC1 with:
0464 // - channels 0 & 1 as single-ended
0465 // - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
0466 #include <dt-bindings/interrupt-controller/arm-gic.h>
0467 #include <dt-bindings/clock/stm32mp1-clks.h>
0468 adc12: adc@48003000 {
0469 compatible = "st,stm32mp1-adc-core";
0470 reg = <0x48003000 0x400>;
0471 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0472 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0473 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
0474 clock-names = "bus", "adc";
0475 booster-supply = <&booster>;
0476 vdd-supply = <&vdd>;
0477 vdda-supply = <&vdda>;
0478 vref-supply = <&vref>;
0479 st,syscfg = <&syscfg>;
0480 interrupt-controller;
0481 #interrupt-cells = <1>;
0482 #address-cells = <1>;
0483 #size-cells = <0>;
0484 adc@0 {
0485 compatible = "st,stm32mp1-adc";
0486 #io-channel-cells = <1>;
0487 reg = <0x0>;
0488 interrupt-parent = <&adc12>;
0489 interrupts = <0>;
0490 st,adc-channels = <0 1>;
0491 st,adc-diff-channels = <2 6>, <3 7>;
0492 st,min-sample-time-nsecs = <5000>;
0493 dmas = <&dmamux1 9 0x400 0x05>;
0494 dma-names = "rx";
0495 };
0496 // ...
0497 // other adc child node follow...
0498 };
0499
0500 - |
0501 // Example 3: with stm32mp157c to setup ADC2 with:
0502 // - internal channels 13, 14, 15.
0503 #include <dt-bindings/interrupt-controller/arm-gic.h>
0504 #include <dt-bindings/clock/stm32mp1-clks.h>
0505 adc122: adc@48003000 {
0506 compatible = "st,stm32mp1-adc-core";
0507 reg = <0x48003000 0x400>;
0508 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0509 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0510 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
0511 clock-names = "bus", "adc";
0512 booster-supply = <&booster>;
0513 vdd-supply = <&vdd>;
0514 vdda-supply = <&vdda>;
0515 vref-supply = <&vref>;
0516 st,syscfg = <&syscfg>;
0517 interrupt-controller;
0518 #interrupt-cells = <1>;
0519 #address-cells = <1>;
0520 #size-cells = <0>;
0521 adc@100 {
0522 compatible = "st,stm32mp1-adc";
0523 #io-channel-cells = <1>;
0524 reg = <0x100>;
0525 interrupts = <1>;
0526 #address-cells = <1>;
0527 #size-cells = <0>;
0528 channel@13 {
0529 reg = <13>;
0530 label = "vrefint";
0531 st,min-sample-time-ns = <9000>;
0532 };
0533 channel@14 {
0534 reg = <14>;
0535 label = "vddcore";
0536 st,min-sample-time-ns = <9000>;
0537 };
0538 channel@15 {
0539 reg = <15>;
0540 label = "vbat";
0541 st,min-sample-time-ns = <9000>;
0542 };
0543 };
0544 };
0545
0546 ...
