iio/adc/renesas%2Crzg2l-adc.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Renesas RZ/G2L ADC
0008
0009 maintainers:
0010   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
0011
0012 description: |
0013   A/D Converter block is a successive approximation analog-to-digital converter
0014   with a 12-bit accuracy. Up to eight analog input channels can be selected.
0015   Conversions can be performed in single or repeat mode. Result of the ADC is
0016   stored in a 32-bit data register corresponding to each channel.
0017
0018 properties:
0019   compatible:
0020     items:
0021       - enum:
0022           - renesas,r9a07g043-adc   # RZ/G2UL
0023           - renesas,r9a07g044-adc   # RZ/G2L
0024           - renesas,r9a07g054-adc   # RZ/V2L
0025       - const: renesas,rzg2l-adc
0026
0027   reg:
0028     maxItems: 1
0029
0030   interrupts:
0031     maxItems: 1
0032
0033   clocks:
0034     items:
0035       - description: converter clock
0036       - description: peripheral clock
0037
0038   clock-names:
0039     items:
0040       - const: adclk
0041       - const: pclk
0042
0043   power-domains:
0044     maxItems: 1
0045
0046   resets:
0047     maxItems: 2
0048
0049   reset-names:
0050     items:
0051       - const: presetn
0052       - const: adrst-n
0053
0054   '#address-cells':
0055     const: 1
0056
0057   '#size-cells':
0058     const: 0
0059
0060 required:
0061   - compatible
0062   - reg
0063   - interrupts
0064   - clocks
0065   - clock-names
0066   - power-domains
0067   - resets
0068   - reset-names
0069
0070 patternProperties:
0071   "^channel@[0-7]$":
0072     $ref: "adc.yaml"
0073     type: object
0074     description: |
0075       Represents the external channels which are connected to the ADC.
0076
0077     properties:
0078       reg:
0079         description: |
0080           The channel number.
0081
0082     required:
0083       - reg
0084
0085     additionalProperties: false
0086
0087 allOf:
0088   - if:
0089       properties:
0090         compatible:
0091           contains:
0092             const: renesas,r9a07g043-adc
0093     then:
0094       patternProperties:
0095         "^channel@[2-7]$": false
0096         "^channel@[0-1]$":
0097           properties:
0098             reg:
0099               minimum: 0
0100               maximum: 1
0101     else:
0102       patternProperties:
0103         "^channel@[0-7]$":
0104           properties:
0105             reg:
0106               minimum: 0
0107               maximum: 7
0108
0109 additionalProperties: false
0110
0111 examples:
0112   - |
0113     #include <dt-bindings/clock/r9a07g044-cpg.h>
0114     #include <dt-bindings/interrupt-controller/arm-gic.h>
0115
0116     adc: adc@10059000 {
0117       compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
0118       reg = <0x10059000 0x400>;
0119       interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
0120       clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
0121                <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
0122       clock-names = "adclk", "pclk";
0123       power-domains = <&cpg>;
0124       resets = <&cpg R9A07G044_ADC_PRESETN>,
0125                <&cpg R9A07G044_ADC_ADRST_N>;
0126       reset-names = "presetn", "adrst-n";
0127
0128       #address-cells = <1>;
0129       #size-cells = <0>;
0130
0131       channel@0 {
0132         reg = <0>;
0133       };
0134       channel@1 {
0135         reg = <1>;
0136       };
0137       channel@2 {
0138         reg = <2>;
0139       };
0140       channel@3 {
0141         reg = <3>;
0142       };
0143       channel@4 {
0144         reg = <4>;
0145       };
0146       channel@5 {
0147         reg = <5>;
0148       };
0149       channel@6 {
0150         reg = <6>;
0151       };
0152       channel@7 {
0153         reg = <7>;
0154       };
0155     };