0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NXP IMX8QXP ADC bindings
0008
0009 maintainers:
0010 - Cai Huoqing <caihuoqing@baidu.com>
0011
0012 description:
0013 Supports the ADC found on the IMX8QXP SoC.
0014
0015 properties:
0016 compatible:
0017 const: nxp,imx8qxp-adc
0018
0019 reg:
0020 maxItems: 1
0021
0022 interrupts:
0023 maxItems: 1
0024
0025 clocks:
0026 maxItems: 2
0027
0028 clock-names:
0029 items:
0030 - const: per
0031 - const: ipg
0032
0033 assigned-clocks:
0034 maxItems: 1
0035
0036 assigned-clock-rates:
0037 maxItems: 1
0038
0039 power-domains:
0040 maxItems: 1
0041
0042 "#io-channel-cells":
0043 const: 1
0044
0045 required:
0046 - compatible
0047 - reg
0048 - interrupts
0049 - clocks
0050 - clock-names
0051 - assigned-clocks
0052 - assigned-clock-rates
0053 - power-domains
0054 - "#io-channel-cells"
0055
0056 additionalProperties: false
0057
0058 examples:
0059 - |
0060 #include <dt-bindings/interrupt-controller/arm-gic.h>
0061 #include <dt-bindings/firmware/imx/rsrc.h>
0062 soc {
0063 #address-cells = <2>;
0064 #size-cells = <2>;
0065 adc@5a880000 {
0066 compatible = "nxp,imx8qxp-adc";
0067 reg = <0x0 0x5a880000 0x0 0x10000>;
0068 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
0069 clocks = <&clk IMX_SC_R_ADC_0>,
0070 <&clk IMX_SC_R_ADC_0>;
0071 clock-names = "per", "ipg";
0072 assigned-clocks = <&clk IMX_SC_R_ADC_0>;
0073 assigned-clock-rates = <24000000>;
0074 power-domains = <&pd IMX_SC_R_ADC_0>;
0075 #io-channel-cells = <1>;
0076 };
0077 };
0078 ...
