0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/iio/adc/fsl,vf610-adc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: ADC found on Freescale vf610 and similar SoCs
0008
0009 maintainers:
0010 - Haibo Chen <haibo.chen@nxp.com>
0011
0012 description:
0013 ADCs found on vf610/i.MX6slx and upward SoCs from Freescale.
0014
0015 properties:
0016 compatible:
0017 oneOf:
0018 - items:
0019 - enum:
0020 - fsl,imx6sx-adc
0021 - fsl,imx6ul-adc
0022 - const: fsl,vf610-adc
0023 - items:
0024 - const: fsl,vf610-adc
0025
0026 reg:
0027 maxItems: 1
0028
0029 interrupts:
0030 maxItems: 1
0031
0032 clocks:
0033 description: ADC source clock (ipg clock)
0034 maxItems: 1
0035
0036 clock-names:
0037 const: adc
0038
0039 vref-supply:
0040 description: ADC reference voltage supply.
0041
0042 fsl,adck-max-frequency:
0043 $ref: /schemas/types.yaml#/definitions/uint32-array
0044 minItems: 3
0045 maxItems: 3
0046 description: |
0047 Maximum frequencies from datasheet operating requirements.
0048 Three values necessary to cover the 3 conversion modes.
0049 * Frequency in normal mode (ADLPC=0, ADHSC=0)
0050 * Frequency in high-speed mode (ADLPC=0, ADHSC=1)
0051 * Frequency in low-power mode (ADLPC=1, ADHSC=0)
0052
0053 min-sample-time:
0054 $ref: /schemas/types.yaml#/definitions/uint32
0055 description:
0056 Minimum sampling time in nanoseconds. This value has
0057 to be chosen according to the conversion mode and the connected analog
0058 source resistance (R_as) and capacitance (C_as). Refer the datasheet's
0059 operating requirements. A safe default across a wide range of R_as and
0060 C_as as well as conversion modes is 1000ns.
0061
0062 "#io-channel-cells":
0063 const: 1
0064
0065 required:
0066 - compatible
0067 - reg
0068 - interrupts
0069 - clocks
0070 - clock-names
0071 - vref-supply
0072
0073 additionalProperties: false
0074
0075 examples:
0076 - |
0077 #include <dt-bindings/clock/vf610-clock.h>
0078 adc@4003b000 {
0079 compatible = "fsl,vf610-adc";
0080 reg = <0x4003b000 0x1000>;
0081 interrupts = <0 53 0x04>;
0082 clocks = <&clks VF610_CLK_ADC0>;
0083 clock-names = "adc";
0084 fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>;
0085 vref-supply = <®_vcc_3v3_mcu>;
0086 min-sample-time = <10000>;
0087 };
0088 ...