0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/iio/adc/atmel,sama5d2-adc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: AT91 SAMA5D2 Analog to Digital Converter (ADC)
0008
0009 maintainers:
0010 - Eugen Hristev <eugen.hristev@microchip.com>
0011
0012 properties:
0013 compatible:
0014 enum:
0015 - atmel,sama5d2-adc
0016 - microchip,sam9x60-adc
0017 - microchip,sama7g5-adc
0018
0019 reg:
0020 maxItems: 1
0021
0022 interrupts:
0023 maxItems: 1
0024
0025 clocks:
0026 maxItems: 1
0027
0028 clock-names:
0029 const: adc_clk
0030
0031 vref-supply: true
0032 vddana-supply: true
0033
0034 atmel,min-sample-rate-hz:
0035 description: Minimum sampling rate, it depends on SoC.
0036
0037 atmel,max-sample-rate-hz:
0038 description: Maximum sampling rate, it depends on SoC.
0039
0040 atmel,startup-time-ms:
0041 description: Startup time expressed in ms, it depends on SoC.
0042
0043 atmel,trigger-edge-type:
0044 $ref: '/schemas/types.yaml#/definitions/uint32'
0045 description:
0046 One of possible edge types for the ADTRG hardware trigger pin.
0047 When the specific edge type is detected, the conversion will
0048 start. Should be one of IRQ_TYPE_EDGE_RISING, IRQ_TYPE_EDGE_FALLING
0049 or IRQ_TYPE_EDGE_BOTH.
0050 enum: [1, 2, 3]
0051
0052 dmas:
0053 maxItems: 1
0054
0055 dma-names:
0056 const: rx
0057
0058 "#io-channel-cells":
0059 const: 1
0060
0061 additionalProperties: false
0062
0063 required:
0064 - compatible
0065 - reg
0066 - interrupts
0067 - clocks
0068 - clock-names
0069 - vref-supply
0070 - vddana-supply
0071 - atmel,min-sample-rate-hz
0072 - atmel,max-sample-rate-hz
0073 - atmel,startup-time-ms
0074
0075 examples:
0076 - |
0077 #include <dt-bindings/dma/at91.h>
0078 #include <dt-bindings/interrupt-controller/irq.h>
0079 soc {
0080 #address-cells = <1>;
0081 #size-cells = <1>;
0082
0083 adc@fc030000 {
0084 compatible = "atmel,sama5d2-adc";
0085 reg = <0xfc030000 0x100>;
0086 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
0087 clocks = <&adc_clk>;
0088 clock-names = "adc_clk";
0089 atmel,min-sample-rate-hz = <200000>;
0090 atmel,max-sample-rate-hz = <20000000>;
0091 atmel,startup-time-ms = <4>;
0092 vddana-supply = <&vdd_3v3_lp_reg>;
0093 vref-supply = <&vdd_3v3_lp_reg>;
0094 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_BOTH>;
0095 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
0096 dma-names = "rx";
0097 #io-channel-cells = <1>;
0098 };
0099 };
0100 ...
