0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Analog Devices AXI ADC IP core
0008
0009 maintainers:
0010 - Michael Hennerich <michael.hennerich@analog.com>
0011
0012 description: |
0013 Analog Devices Generic AXI ADC IP core for interfacing an ADC device
0014 with a high speed serial (JESD204B/C) or source synchronous parallel
0015 interface (LVDS/CMOS).
0016 Usually, some other interface type (i.e SPI) is used as a control
0017 interface for the actual ADC, while this IP core will interface
0018 to the data-lines of the ADC and handle the streaming of data into
0019 memory via DMA.
0020
0021 https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
0022
0023 properties:
0024 compatible:
0025 enum:
0026 - adi,axi-adc-10.0.a
0027
0028 reg:
0029 maxItems: 1
0030
0031 dmas:
0032 maxItems: 1
0033
0034 dma-names:
0035 items:
0036 - const: rx
0037
0038 adi,adc-dev:
0039 $ref: /schemas/types.yaml#/definitions/phandle
0040 description:
0041 A reference to a the actual ADC to which this FPGA ADC interfaces to.
0042
0043 required:
0044 - compatible
0045 - dmas
0046 - reg
0047 - adi,adc-dev
0048
0049 additionalProperties: false
0050
0051 examples:
0052 - |
0053 axi-adc@44a00000 {
0054 compatible = "adi,axi-adc-10.0.a";
0055 reg = <0x44a00000 0x10000>;
0056 dmas = <&rx_dma 0>;
0057 dma-names = "rx";
0058
0059 adi,adc-dev = <&spi_adc>;
0060 };
0061 ...
