0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: I2C controller embedded in STMicroelectronics STM32 I2C platform
0008
0009 maintainers:
0010 - Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
0011
0012 allOf:
0013 - $ref: /schemas/i2c/i2c-controller.yaml#
0014 - if:
0015 properties:
0016 compatible:
0017 contains:
0018 enum:
0019 - st,stm32f7-i2c
0020 - st,stm32mp13-i2c
0021 - st,stm32mp15-i2c
0022 then:
0023 properties:
0024 i2c-scl-rising-time-ns:
0025 default: 25
0026
0027 i2c-scl-falling-time-ns:
0028 default: 10
0029 else:
0030 properties:
0031 st,syscfg-fmp: false
0032
0033 - if:
0034 properties:
0035 compatible:
0036 contains:
0037 enum:
0038 - st,stm32f4-i2c
0039 then:
0040 properties:
0041 clock-frequency:
0042 enum: [100000, 400000]
0043
0044 properties:
0045 compatible:
0046 enum:
0047 - st,stm32f4-i2c
0048 - st,stm32f7-i2c
0049 - st,stm32mp13-i2c
0050 - st,stm32mp15-i2c
0051
0052 reg:
0053 maxItems: 1
0054
0055 interrupts:
0056 items:
0057 - description: interrupt ID for I2C event
0058 - description: interrupt ID for I2C error
0059
0060 interrupt-names:
0061 items:
0062 - const: event
0063 - const: error
0064
0065 resets:
0066 maxItems: 1
0067
0068 clocks:
0069 maxItems: 1
0070
0071 dmas:
0072 items:
0073 - description: RX DMA Channel phandle
0074 - description: TX DMA Channel phandle
0075
0076 dma-names:
0077 items:
0078 - const: rx
0079 - const: tx
0080
0081 clock-frequency:
0082 description: Desired I2C bus clock frequency in Hz. If not specified,
0083 the default 100 kHz frequency will be used.
0084 For STM32F7, STM32H7 and STM32MP1 SoCs, if timing parameters
0085 match, the bus clock frequency can be from 1Hz to 1MHz.
0086 default: 100000
0087 minimum: 1
0088 maximum: 1000000
0089
0090 st,syscfg-fmp:
0091 description: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode
0092 Plus speed is selected by slave.
0093 $ref: "/schemas/types.yaml#/definitions/phandle-array"
0094 items:
0095 - items:
0096 - description: phandle to syscfg
0097 - description: register offset within syscfg
0098 - description: register bitmask for FMP bit
0099
0100 wakeup-source: true
0101
0102 required:
0103 - compatible
0104 - reg
0105 - interrupts
0106 - resets
0107 - clocks
0108
0109 unevaluatedProperties: false
0110
0111 examples:
0112 - |
0113 #include <dt-bindings/mfd/stm32f7-rcc.h>
0114 #include <dt-bindings/clock/stm32fx-clock.h>
0115 //Example 1 (with st,stm32f4-i2c compatible)
0116 i2c@40005400 {
0117 compatible = "st,stm32f4-i2c";
0118 #address-cells = <1>;
0119 #size-cells = <0>;
0120 reg = <0x40005400 0x400>;
0121 interrupts = <31>,
0122 <32>;
0123 resets = <&rcc 277>;
0124 clocks = <&rcc 0 149>;
0125 };
0126
0127 - |
0128 #include <dt-bindings/mfd/stm32f7-rcc.h>
0129 #include <dt-bindings/clock/stm32fx-clock.h>
0130 //Example 2 (with st,stm32f7-i2c compatible)
0131 i2c@40005800 {
0132 compatible = "st,stm32f7-i2c";
0133 #address-cells = <1>;
0134 #size-cells = <0>;
0135 reg = <0x40005800 0x400>;
0136 interrupts = <31>,
0137 <32>;
0138 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
0139 clocks = <&rcc 1 CLK_I2C1>;
0140 };
0141
0142 - |
0143 #include <dt-bindings/mfd/stm32f7-rcc.h>
0144 #include <dt-bindings/clock/stm32fx-clock.h>
0145 //Example 3 (with st,stm32mp15-i2c compatible on stm32mp)
0146 #include <dt-bindings/interrupt-controller/arm-gic.h>
0147 #include <dt-bindings/clock/stm32mp1-clks.h>
0148 #include <dt-bindings/reset/stm32mp1-resets.h>
0149 i2c@40013000 {
0150 compatible = "st,stm32mp15-i2c";
0151 #address-cells = <1>;
0152 #size-cells = <0>;
0153 reg = <0x40013000 0x400>;
0154 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0155 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0156 clocks = <&rcc I2C2_K>;
0157 resets = <&rcc I2C2_R>;
0158 i2c-scl-rising-time-ns = <185>;
0159 i2c-scl-falling-time-ns = <20>;
0160 st,syscfg-fmp = <&syscfg 0x4 0x2>;
0161 };
