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0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006 
0007 title: OpenCores I2C controller
0008 
0009 maintainers:
0010   - Peter Korsgaard <peter@korsgaard.com>
0011   - Andrew Lunn <andrew@lunn.ch>
0012 
0013 allOf:
0014   - $ref: /schemas/i2c/i2c-controller.yaml#
0015 
0016 properties:
0017   compatible:
0018     oneOf:
0019       - items:
0020           - enum:
0021               - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
0022               - sifive,fu540-c000-i2c # Opencore based IP block FU540-C000 SoC
0023           - const: sifive,i2c0
0024       - enum:
0025           - opencores,i2c-ocores
0026           - aeroflexgaisler,i2cmst
0027 
0028   reg:
0029     maxItems: 1
0030 
0031   interrupts:
0032     maxItems: 1
0033 
0034   clocks:
0035     maxItems: 1
0036 
0037   clock-frequency:
0038     description: |
0039       clock-frequency property is meant to control the bus frequency for i2c bus
0040       drivers, but it was incorrectly used to specify i2c controller input clock
0041       frequency. So the following rules are set to fix this situation:
0042       - if clock-frequency is present and neither opencores,ip-clock-frequency nor
0043         clocks are, then clock-frequency specifies i2c controller clock frequency.
0044         This is to keep backwards compatibility with setups using old DTB. i2c bus
0045         frequency is fixed at 100 KHz.
0046       - if clocks is present it specifies i2c controller clock. clock-frequency
0047         property specifies i2c bus frequency.
0048       - if opencores,ip-clock-frequency is present it specifies i2c controller
0049         clock frequency. clock-frequency property specifies i2c bus frequency.
0050     default: 100000
0051 
0052   reg-io-width:
0053     description: |
0054       io register width in bytes
0055     enum: [1, 2, 4]
0056 
0057   reg-shift:
0058     description: |
0059       device register offsets are shifted by this value
0060     default: 0
0061 
0062   regstep:
0063     description: |
0064       deprecated, use reg-shift above
0065     deprecated: true
0066 
0067   opencores,ip-clock-frequency:
0068     $ref: /schemas/types.yaml#/definitions/uint32
0069     description: |
0070       Frequency of the controller clock in Hz. Mutually exclusive with clocks.
0071       See the note above.
0072 
0073 required:
0074   - compatible
0075   - reg
0076   - "#address-cells"
0077   - "#size-cells"
0078 
0079 oneOf:
0080   - required:
0081       - opencores,ip-clock-frequency
0082   - required:
0083       - clocks
0084 
0085 unevaluatedProperties: false
0086 
0087 examples:
0088   - |
0089     i2c@a0000000 {
0090       compatible = "opencores,i2c-ocores";
0091       reg = <0xa0000000 0x8>;
0092       #address-cells = <1>;
0093       #size-cells = <0>;
0094       interrupts = <10>;
0095       opencores,ip-clock-frequency = <20000000>;
0096 
0097       reg-shift = <0>;  /* 8 bit registers */
0098       reg-io-width = <1>;       /* 8 bit read/write */
0099     };
0100 
0101     i2c@b0000000 {
0102       compatible = "opencores,i2c-ocores";
0103       reg = <0xa0000000 0x8>;
0104       #address-cells = <1>;
0105       #size-cells = <0>;
0106       interrupts = <10>;
0107       clocks = <&osc>;
0108       clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
0109 
0110       reg-shift = <0>;  /* 8 bit registers */
0111       reg-io-width = <1>;       /* 8 bit read/write */
0112     };
0113 ...