0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 maintainers:
0008 - Thierry Reding <thierry.reding@gmail.com>
0009 - Jon Hunter <jonathanh@nvidia.com>
0010
0011 title: NVIDIA Tegra I2C controller driver
0012
0013 properties:
0014 compatible:
0015 oneOf:
0016 - description: Tegra20 has 4 generic I2C controller. This can support
0017 master and slave mode of I2C communication. The i2c-tegra driver
0018 only support master mode of I2C communication. Driver of I2C
0019 controller is only compatible with "nvidia,tegra20-i2c".
0020 const: nvidia,tegra20-i2c
0021 - description: Tegra20 has specific I2C controller called as DVC I2C
0022 controller. This only support master mode of I2C communication.
0023 Register interface/offset and interrupts handling are different than
0024 generic I2C controller. Driver of DVC I2C controller is only
0025 compatible with "nvidia,tegra20-i2c-dvc".
0026 const: nvidia,tegra20-i2c-dvc
0027 - description: |
0028 Tegra30 has 5 generic I2C controller. This controller is very much
0029 similar to Tegra20 I2C controller with additional feature: Continue
0030 Transfer Support. This feature helps to implement M_NO_START as per
0031 I2C core API transfer flags. Driver of I2C controller is compatible
0032 with "nvidia,tegra30-i2c" to enable the continue transfer support.
0033 This is also compatible with "nvidia,tegra20-i2c" without continue
0034 transfer support.
0035 items:
0036 - const: nvidia,tegra30-i2c
0037 - const: nvidia,tegra20-i2c
0038 - description: |
0039 Tegra114 has 5 generic I2C controllers. This controller is very much
0040 similar to Tegra30 I2C controller with some hardware modification:
0041 - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk
0042 and fast-clk. Tegra114 has only one clock source called as
0043 div-clk and hence clock mechanism is changed in I2C controller.
0044 - Tegra30/Tegra20 I2C controller has enabled per packet transfer
0045 by default and there is no way to disable it. Tegra114 has this
0046 interrupt disable by default and SW need to enable explicitly.
0047 Due to above changes, Tegra114 I2C driver makes incompatible with
0048 previous hardware driver. Hence, Tegra114 I2C controller is
0049 compatible with "nvidia,tegra114-i2c".
0050 const: nvidia,tegra114-i2c
0051 - description: |
0052 Tegra124 has 6 generic I2C controllers. These controllers are very
0053 similar to those found on Tegra114 but also contain several hardware
0054 improvements and new registers.
0055 const: nvidia,tegra124-i2c
0056 - description: |
0057 Tegra210 has 6 generic I2C controllers. These controllers are very
0058 similar to those found on Tegra124.
0059 items:
0060 - const: nvidia,tegra210-i2c
0061 - const: nvidia,tegra124-i2c
0062 - description: |
0063 Tegra210 has one I2C controller that is on host1x bus and is part of
0064 the VE power domain and typically used for camera use-cases. This VI
0065 I2C controller is mostly compatible with the programming model of
0066 the regular I2C controllers with a few exceptions. The I2C registers
0067 start at an offset of 0xc00 (instead of 0), registers are 16 bytes
0068 apart (rather than 4) and the controller does not support slave
0069 mode.
0070 const: nvidia,tegra210-i2c-vi
0071 - description: |
0072 Tegra186 has 9 generic I2C controllers, two of which are in the AON
0073 (always-on) partition of the SoC. All of these controllers are very
0074 similar to those found on Tegra210.
0075 const: nvidia,tegra186-i2c
0076 - description: |
0077 Tegra194 has 8 generic I2C controllers, two of which are in the AON
0078 (always-on) partition of the SoC. All of these controllers are very
0079 similar to those found on Tegra186. However, these controllers have
0080 support for 64 KiB transactions whereas earlier chips supported no
0081 more than 4 KiB per transactions.
0082 const: nvidia,tegra194-i2c
0083
0084 reg:
0085 maxItems: 1
0086
0087 interrupts:
0088 maxItems: 1
0089
0090 '#address-cells':
0091 const: 1
0092
0093 '#size-cells':
0094 const: 0
0095
0096 clocks:
0097 minItems: 1
0098 maxItems: 2
0099
0100 clock-names:
0101 minItems: 1
0102 maxItems: 2
0103
0104 resets:
0105 items:
0106 - description: module reset
0107
0108 reset-names:
0109 items:
0110 - const: i2c
0111
0112 dmas:
0113 items:
0114 - description: DMA channel for the reception FIFO
0115 - description: DMA channel for the transmission FIFO
0116
0117 dma-names:
0118 items:
0119 - const: rx
0120 - const: tx
0121
0122 allOf:
0123 - $ref: /schemas/i2c/i2c-controller.yaml
0124 - if:
0125 properties:
0126 compatible:
0127 contains:
0128 enum:
0129 - nvidia,tegra20-i2c
0130 - nvidia,tegra30-i2c
0131 then:
0132 properties:
0133 clock-names:
0134 items:
0135 - const: div-clk
0136 - const: fast-clk
0137
0138 - if:
0139 properties:
0140 compatible:
0141 contains:
0142 const: nvidia,tegra114-i2c
0143 then:
0144 properties:
0145 clock-names:
0146 items:
0147 - const: div-clk
0148
0149 - if:
0150 properties:
0151 compatible:
0152 contains:
0153 const: nvidia,tegra210-i2c
0154 then:
0155 properties:
0156 clock-names:
0157 items:
0158 - const: div-clk
0159
0160 - if:
0161 properties:
0162 compatible:
0163 contains:
0164 const: nvidia,tegra210-i2c-vi
0165 then:
0166 properties:
0167 clock-names:
0168 items:
0169 - const: div-clk
0170 - const: slow
0171 power-domains:
0172 items:
0173 - description: phandle to the VENC power domain
0174
0175 unevaluatedProperties: false
0176
0177 examples:
0178 - |
0179 i2c@7000c000 {
0180 compatible = "nvidia,tegra20-i2c";
0181 reg = <0x7000c000 0x100>;
0182 interrupts = <0 38 0x04>;
0183 clocks = <&tegra_car 12>, <&tegra_car 124>;
0184 clock-names = "div-clk", "fast-clk";
0185 resets = <&tegra_car 12>;
0186 reset-names = "i2c";
0187 dmas = <&apbdma 16>, <&apbdma 16>;
0188 dma-names = "rx", "tx";
0189
0190 #address-cells = <1>;
0191 #size-cells = <0>;
0192 };
