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OSCL-LXR

 
 

    


0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/i2c/microchip,corei2c.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006 
0007 title: Microchip MPFS I2C Controller Device Tree Bindings
0008 
0009 maintainers:
0010   - Daire McNamara <daire.mcnamara@microchip.com>
0011 
0012 allOf:
0013   - $ref: /schemas/i2c/i2c-controller.yaml#
0014 
0015 properties:
0016   compatible:
0017     oneOf:
0018       - items:
0019           - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
0020           - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
0021       - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
0022 
0023   reg:
0024     maxItems: 1
0025 
0026   interrupts:
0027     maxItems: 1
0028 
0029   clocks:
0030     maxItems: 1
0031 
0032   clock-frequency:
0033     description: |
0034       Desired I2C bus clock frequency in Hz. As only Standard and Fast
0035       modes are supported, possible values are 100000 and 400000.
0036     enum: [100000, 400000]
0037 
0038 required:
0039   - compatible
0040   - reg
0041   - interrupts
0042   - clocks
0043 
0044 unevaluatedProperties: false
0045 
0046 examples:
0047   - |
0048     i2c@2010a000 {
0049       compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
0050       reg = <0x2010a000 0x1000>;
0051       clocks = <&clkcfg 15>;
0052       interrupt-parent = <&plic>;
0053       interrupts = <58>;
0054       clock-frequency = <100000>;
0055     };
0056 ...