0001 * Altera I2C Controller
0002 * This is Altera's synthesizable logic block I2C Controller for use
0003 * in Altera's FPGAs.
0004
0005 Required properties :
0006 - compatible : should be "altr,softip-i2c-v1.0"
0007 - reg : Offset and length of the register set for the device
0008 - interrupts : <IRQ> where IRQ is the interrupt number.
0009 - clocks : phandle to input clock.
0010 - #address-cells = <1>;
0011 - #size-cells = <0>;
0012
0013 Recommended properties :
0014 - clock-frequency : desired I2C bus clock frequency in Hz.
0015
0016 Optional properties :
0017 - fifo-size : Size of the RX and TX FIFOs in bytes.
0018 - Child nodes conforming to i2c bus binding
0019
0020 Example :
0021
0022 i2c@100080000 {
0023 compatible = "altr,softip-i2c-v1.0";
0024 reg = <0x00000001 0x00080000 0x00000040>;
0025 interrupt-parent = <&intc>;
0026 interrupts = <0 43 4>;
0027 clocks = <&clk_0>;
0028 clock-frequency = <100000>;
0029 #address-cells = <1>;
0030 #size-cells = <0>;
0031 fifo-size = <4>;
0032
0033 eeprom@51 {
0034 compatible = "atmel,24c32";
0035 reg = <0x51>;
0036 pagesize = <32>;
0037 };
0038 };
0039
