0001 NVIDIA Tegra Graphics Processing Units
0002
0003 Required properties:
0004 - compatible: "nvidia,<gpu>"
0005 Currently recognized values:
0006 - nvidia,gk20a
0007 - nvidia,gm20b
0008 - nvidia,gp10b
0009 - nvidia,gv11b
0010 - reg: Physical base address and length of the controller's registers.
0011 Must contain two entries:
0012 - first entry for bar0
0013 - second entry for bar1
0014 - interrupts: Must contain an entry for each entry in interrupt-names.
0015 See ../interrupt-controller/interrupts.txt for details.
0016 - interrupt-names: Must include the following entries:
0017 - stall
0018 - nonstall
0019 - vdd-supply: regulator for supply voltage. Only required for GPUs not using
0020 power domains.
0021 - clocks: Must contain an entry for each entry in clock-names.
0022 See ../clocks/clock-bindings.txt for details.
0023 - clock-names: Must include the following entries:
0024 - gpu
0025 - pwr
0026 If the compatible string is "nvidia,gm20b", then the following clock
0027 is also required:
0028 - ref
0029 If the compatible string is "nvidia,gv11b", then the following clock is also
0030 required:
0031 - fuse
0032 - resets: Must contain an entry for each entry in reset-names.
0033 See ../reset/reset.txt for details.
0034 - reset-names: Must include the following entries:
0035 - gpu
0036 - power-domains: GPUs that make use of power domains can define this property
0037 instead of vdd-supply. Currently "nvidia,gp10b" makes use of this.
0038
0039 Optional properties:
0040 - iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
0041
0042 Example for GK20A:
0043
0044 gpu@57000000 {
0045 compatible = "nvidia,gk20a";
0046 reg = <0x0 0x57000000 0x0 0x01000000>,
0047 <0x0 0x58000000 0x0 0x01000000>;
0048 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
0049 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
0050 interrupt-names = "stall", "nonstall";
0051 vdd-supply = <&vdd_gpu>;
0052 clocks = <&tegra_car TEGRA124_CLK_GPU>,
0053 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
0054 clock-names = "gpu", "pwr";
0055 resets = <&tegra_car 184>;
0056 reset-names = "gpu";
0057 iommus = <&mc TEGRA_SWGROUP_GPU>;
0058 };
0059
0060 Example for GM20B:
0061
0062 gpu@57000000 {
0063 compatible = "nvidia,gm20b";
0064 reg = <0x0 0x57000000 0x0 0x01000000>,
0065 <0x0 0x58000000 0x0 0x01000000>;
0066 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
0067 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
0068 interrupt-names = "stall", "nonstall";
0069 clocks = <&tegra_car TEGRA210_CLK_GPU>,
0070 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
0071 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
0072 clock-names = "gpu", "pwr", "ref";
0073 resets = <&tegra_car 184>;
0074 reset-names = "gpu";
0075 iommus = <&mc TEGRA_SWGROUP_GPU>;
0076 };
0077
0078 Example for GP10B:
0079
0080 gpu@17000000 {
0081 compatible = "nvidia,gp10b";
0082 reg = <0x0 0x17000000 0x0 0x1000000>,
0083 <0x0 0x18000000 0x0 0x1000000>;
0084 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
0085 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0086 interrupt-names = "stall", "nonstall";
0087 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
0088 <&bpmp TEGRA186_CLK_GPU>;
0089 clock-names = "gpu", "pwr";
0090 resets = <&bpmp TEGRA186_RESET_GPU>;
0091 reset-names = "gpu";
0092 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
0093 iommus = <&smmu TEGRA186_SID_GPU>;
0094 };
0095
0096 Example for GV11B:
0097
0098 gpu@17000000 {
0099 compatible = "nvidia,gv11b";
0100 reg = <0x17000000 0x1000000>,
0101 <0x18000000 0x1000000>;
0102 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0103 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0104 interrupt-names = "stall", "nonstall";
0105 clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
0106 <&bpmp TEGRA194_CLK_GPU_PWR>,
0107 <&bpmp TEGRA194_CLK_FUSE>;
0108 clock-names = "gpu", "pwr", "fuse";
0109 resets = <&bpmp TEGRA194_RESET_GPU>;
0110 reset-names = "gpu";
0111 dma-coherent;
0112
0113 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
0114 iommus = <&smmu TEGRA194_SID_GPU>;
0115 };
