gpu/host1x/nvidia%2Ctegra210-nvenc.yaml

0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: Device tree binding for NVIDIA Tegra NVENC
0008
0009 description: |
0010   NVENC is the hardware video encoder present on NVIDIA Tegra210
0011   and newer chips. It is located on the Host1x bus and typically
0012   programmed through Host1x channels.
0013
0014 maintainers:
0015   - Thierry Reding <treding@gmail.com>
0016   - Mikko Perttunen <mperttunen@nvidia.com>
0017
0018 properties:
0019   $nodename:
0020     pattern: "^nvenc@[0-9a-f]*$"
0021
0022   compatible:
0023     enum:
0024       - nvidia,tegra210-nvenc
0025       - nvidia,tegra186-nvenc
0026       - nvidia,tegra194-nvenc
0027
0028   reg:
0029     maxItems: 1
0030
0031   clocks:
0032     maxItems: 1
0033
0034   clock-names:
0035     items:
0036       - const: nvenc
0037
0038   resets:
0039     maxItems: 1
0040
0041   reset-names:
0042     items:
0043       - const: nvenc
0044
0045   power-domains:
0046     maxItems: 1
0047
0048   iommus:
0049     maxItems: 1
0050
0051   dma-coherent: true
0052
0053   interconnects:
0054     minItems: 2
0055     maxItems: 3
0056
0057   interconnect-names:
0058     minItems: 2
0059     maxItems: 3
0060
0061   nvidia,host1x-class:
0062     description: |
0063       Host1x class of the engine, used to specify the targeted engine
0064       when programming the engine through Host1x channels or when
0065       configuring engine-specific behavior in Host1x.
0066     default: 0x21
0067     $ref: /schemas/types.yaml#/definitions/uint32
0068
0069 required:
0070   - compatible
0071   - reg
0072   - clocks
0073   - clock-names
0074   - resets
0075   - reset-names
0076   - power-domains
0077
0078 allOf:
0079   - if:
0080       properties:
0081         compatible:
0082           enum:
0083             - nvidia,tegra210-nvenc
0084             - nvidia,tegra186-nvenc
0085     then:
0086       properties:
0087         interconnects:
0088           items:
0089             - description: DMA read memory client
0090             - description: DMA write memory client
0091         interconnect-names:
0092           items:
0093             - const: dma-mem
0094             - const: write
0095   - if:
0096       properties:
0097         compatible:
0098           enum:
0099             - nvidia,tegra194-nvenc
0100     then:
0101       properties:
0102         interconnects:
0103           items:
0104             - description: DMA read memory client
0105             - description: DMA read 2 memory client
0106             - description: DMA write memory client
0107         interconnect-names:
0108           items:
0109             - const: dma-mem
0110             - const: read-1
0111             - const: write
0112
0113 additionalProperties: false
0114
0115 examples:
0116   - |
0117     #include <dt-bindings/clock/tegra186-clock.h>
0118     #include <dt-bindings/memory/tegra186-mc.h>
0119     #include <dt-bindings/power/tegra186-powergate.h>
0120     #include <dt-bindings/reset/tegra186-reset.h>
0121
0122     nvenc@154c0000 {
0123             compatible = "nvidia,tegra186-nvenc";
0124             reg = <0x154c0000 0x40000>;
0125             clocks = <&bpmp TEGRA186_CLK_NVENC>;
0126             clock-names = "nvenc";
0127             resets = <&bpmp TEGRA186_RESET_NVENC>;
0128             reset-names = "nvenc";
0129
0130             power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
0131             interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
0132                             <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
0133             interconnect-names = "dma-mem", "write";
0134             iommus = <&smmu TEGRA186_SID_NVENC>;
0135     };