gpu/host1x/nvidia%2Ctegra210-nvdec.yaml

0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: Device tree binding for NVIDIA Tegra NVDEC
0008
0009 description: |
0010   NVDEC is the hardware video decoder present on NVIDIA Tegra210
0011   and newer chips. It is located on the Host1x bus and typically
0012   programmed through Host1x channels.
0013
0014 maintainers:
0015   - Thierry Reding <treding@gmail.com>
0016   - Mikko Perttunen <mperttunen@nvidia.com>
0017
0018 properties:
0019   $nodename:
0020     pattern: "^nvdec@[0-9a-f]*$"
0021
0022   compatible:
0023     enum:
0024       - nvidia,tegra210-nvdec
0025       - nvidia,tegra186-nvdec
0026       - nvidia,tegra194-nvdec
0027
0028   reg:
0029     maxItems: 1
0030
0031   clocks:
0032     maxItems: 1
0033
0034   clock-names:
0035     items:
0036       - const: nvdec
0037
0038   resets:
0039     maxItems: 1
0040
0041   reset-names:
0042     items:
0043       - const: nvdec
0044
0045   power-domains:
0046     maxItems: 1
0047
0048   iommus:
0049     maxItems: 1
0050
0051   dma-coherent: true
0052
0053   interconnects:
0054     items:
0055       - description: DMA read memory client
0056       - description: DMA read 2 memory client
0057       - description: DMA write memory client
0058
0059   interconnect-names:
0060     items:
0061       - const: dma-mem
0062       - const: read-1
0063       - const: write
0064
0065   nvidia,host1x-class:
0066     description: |
0067       Host1x class of the engine, used to specify the targeted engine
0068       when programming the engine through Host1x channels or when
0069       configuring engine-specific behavior in Host1x.
0070     default: 0xf0
0071     $ref: /schemas/types.yaml#/definitions/uint32
0072
0073 required:
0074   - compatible
0075   - reg
0076   - clocks
0077   - clock-names
0078   - resets
0079   - reset-names
0080   - power-domains
0081
0082 additionalProperties: false
0083
0084 examples:
0085   - |
0086     #include <dt-bindings/clock/tegra186-clock.h>
0087     #include <dt-bindings/interrupt-controller/arm-gic.h>
0088     #include <dt-bindings/memory/tegra186-mc.h>
0089     #include <dt-bindings/power/tegra186-powergate.h>
0090     #include <dt-bindings/reset/tegra186-reset.h>
0091
0092     nvdec@15480000 {
0093             compatible = "nvidia,tegra186-nvdec";
0094             reg = <0x15480000 0x40000>;
0095             clocks = <&bpmp TEGRA186_CLK_NVDEC>;
0096             clock-names = "nvdec";
0097             resets = <&bpmp TEGRA186_RESET_NVDEC>;
0098             reset-names = "nvdec";
0099
0100             power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
0101             interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
0102                             <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
0103                             <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
0104             interconnect-names = "dma-mem", "read-1", "write";
0105             iommus = <&smmu TEGRA186_SID_NVDEC>;
0106     };