0001 === ST Microelectronics SPEAr SPI CS Driver ===
0002
0003 SPEAr platform provides a provision to control chipselects of ARM PL022 Prime
0004 Cell spi controller through its system registers, which otherwise remains under
0005 PL022 control. If chipselect remain under PL022 control then they would be
0006 released as soon as transfer is over and TxFIFO becomes empty. This is not
0007 desired by some of the device protocols above spi which expect (multiple)
0008 transfers without releasing their chipselects.
0009
0010 Chipselects can be controlled by software by turning them as GPIOs. SPEAr
0011 provides another interface through system registers through which software can
0012 directly control each PL022 chipselect. Hence, it is natural for SPEAr to export
0013 the control of this interface as gpio.
0014
0015 Required properties:
0016
0017 * compatible: should be defined as "st,spear-spics-gpio"
0018 * reg: mentioning address range of spics controller
0019 * st-spics,peripcfg-reg: peripheral configuration register offset
0020 * st-spics,sw-enable-bit: bit offset to enable sw control
0021 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
0022 * st-spics,cs-enable-mask: chip select number bit mask
0023 * st-spics,cs-enable-shift: chip select number program offset
0024 * gpio-controller: Marks the device node as gpio controller
0025 * #gpio-cells: should be 1 and will mention chip select number
0026
0027 All the above bit offsets are within peripcfg register.
0028
0029 Example:
0030 -------
0031 spics: spics@e0700000{
0032 compatible = "st,spear-spics-gpio";
0033 reg = <0xe0700000 0x1000>;
0034 st-spics,peripcfg-reg = <0x3b0>;
0035 st-spics,sw-enable-bit = <12>;
0036 st-spics,cs-value-bit = <11>;
0037 st-spics,cs-enable-mask = <3>;
0038 st-spics,cs-enable-shift = <8>;
0039 gpio-controller;
0040 #gpio-cells = <2>;
0041 };
0042
0043
0044 spi0: spi@e0100000 {
0045 num-cs = <3>;
0046 cs-gpios = <&gpio1 7 0>, <&spics 0>,
0047 <&spics 1>;
0048 ...
0049 }
