0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Rockchip GPIO bank
0008
0009 maintainers:
0010 - Heiko Stuebner <heiko@sntech.de>
0011
0012 properties:
0013 compatible:
0014 enum:
0015 - rockchip,gpio-bank
0016 - rockchip,rk3188-gpio-bank0
0017
0018 reg:
0019 maxItems: 1
0020
0021 interrupts:
0022 maxItems: 1
0023
0024 clocks:
0025 minItems: 1
0026 items:
0027 - description: APB interface clock source
0028 - description: GPIO debounce reference clock source
0029
0030 gpio-ranges: true
0031
0032 gpio-controller: true
0033
0034 gpio-line-names: true
0035
0036 "#gpio-cells":
0037 const: 2
0038
0039 interrupt-controller: true
0040
0041 "#interrupt-cells":
0042 const: 2
0043
0044 required:
0045 - compatible
0046 - reg
0047 - interrupts
0048 - clocks
0049 - gpio-controller
0050 - "#gpio-cells"
0051 - interrupt-controller
0052 - "#interrupt-cells"
0053
0054 additionalProperties: false
0055
0056 examples:
0057 - |
0058 #include <dt-bindings/interrupt-controller/arm-gic.h>
0059 pinctrl: pinctrl {
0060 #address-cells = <1>;
0061 #size-cells = <1>;
0062 ranges;
0063
0064 gpio0: gpio@2000a000 {
0065 compatible = "rockchip,rk3188-gpio-bank0";
0066 reg = <0x2000a000 0x100>;
0067 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0068 clocks = <&clk_gates8 9>;
0069
0070 gpio-controller;
0071 #gpio-cells = <2>;
0072
0073 interrupt-controller;
0074 #interrupt-cells = <2>;
0075 };
0076
0077 gpio1: gpio@2003c000 {
0078 compatible = "rockchip,gpio-bank";
0079 reg = <0x2003c000 0x100>;
0080 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0081 clocks = <&clk_gates8 10>;
0082
0083 gpio-controller;
0084 #gpio-cells = <2>;
0085
0086 interrupt-controller;
0087 #interrupt-cells = <2>;
0088 };
0089 };
