0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra GPIO Controller (Tegra186 and later)
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 description: |
0014 Tegra186 contains two GPIO controllers; a main controller and an "AON"
0015 controller. This binding document applies to both controllers. The register
0016 layouts for the controllers share many similarities, but also some
0017 significant differences. Hence, this document describes closely related but
0018 different bindings and compatible values.
0019
0020 The Tegra186 GPIO controller allows software to set the IO direction of,
0021 and read/write the value of, numerous GPIO signals. Routing of GPIO signals
0022 to package balls is under the control of a separate pin controller hardware
0023 block. Two major sets of registers exist:
0024
0025 a) Security registers, which allow configuration of allowed access to the
0026 GPIO register set. These registers exist in a single contiguous block
0027 of physical address space. The size of this block, and the security
0028 features available, varies between the different GPIO controllers.
0029
0030 Access to this set of registers is not necessary in all circumstances.
0031 Code that wishes to configure access to the GPIO registers needs access
0032 to these registers to do so. Code which simply wishes to read or write
0033 GPIO data does not need access to these registers.
0034
0035 b) GPIO registers, which allow manipulation of the GPIO signals. In some
0036 GPIO controllers, these registers are exposed via multiple "physical
0037 aliases" in address space, each of which access the same underlying
0038 state. See the hardware documentation for rationale. Any particular
0039 GPIO client is expected to access just one of these physical aliases.
0040
0041 Tegra HW documentation describes a unified naming convention for all GPIOs
0042 implemented by the SoC. Each GPIO is assigned to a port, and a port may
0043 control a number of GPIOs. Thus, each GPIO is named according to an
0044 alphabetical port name and an integer GPIO name within the port. For
0045 example, GPIO_PA0, GPIO_PN6, or GPIO_PCC3.
0046
0047 The number of ports implemented by each GPIO controller varies. The number
0048 of implemented GPIOs within each port varies. GPIO registers within a
0049 controller are grouped and laid out according to the port they affect.
0050
0051 The mapping from port name to the GPIO controller that implements that
0052 port, and the mapping from port name to register offset within a
0053 controller, are both extremely non-linear. The header file
0054 <dt-bindings/gpio/tegra186-gpio.h> describes the port-level mapping. In
0055 that file, the naming convention for ports matches the HW documentation.
0056 The values chosen for the names are alphabetically sorted within a
0057 particular controller. Drivers need to map between the DT GPIO IDs and HW
0058 register offsets using a lookup table.
0059
0060 Each GPIO controller can generate a number of interrupt signals. Each
0061 signal represents the aggregate status for all GPIOs within a set of
0062 ports. Thus, the number of interrupt signals generated by a controller
0063 varies as a rough function of the number of ports it implements. Note
0064 that the HW documentation refers to both the overall controller HW
0065 module and the sets-of-ports as "controllers".
0066
0067 Each GPIO controller in fact generates multiple interrupts signals for
0068 each set of ports. Each GPIO may be configured to feed into a specific
0069 one of the interrupt signals generated by a set-of-ports. The intent is
0070 for each generated signal to be routed to a different CPU, thus allowing
0071 different CPUs to each handle subsets of the interrupts within a port.
0072 The status of each of these per-port-set signals is reported via a
0073 separate register. Thus, a driver needs to know which status register to
0074 observe. This binding currently defines no configuration mechanism for
0075 this. By default, drivers should use register
0076 GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
0077 define a property to configure this.
0078
0079 properties:
0080 compatible:
0081 enum:
0082 - nvidia,tegra186-gpio
0083 - nvidia,tegra186-gpio-aon
0084 - nvidia,tegra194-gpio
0085 - nvidia,tegra194-gpio-aon
0086 - nvidia,tegra234-gpio
0087 - nvidia,tegra234-gpio-aon
0088
0089 reg-names:
0090 items:
0091 - const: security
0092 - const: gpio
0093 minItems: 1
0094
0095 reg:
0096 items:
0097 - description: Security configuration registers.
0098 - description: |
0099 GPIO control registers. This may cover either:
0100
0101 a) The single physical alias that this OS should use.
0102 b) All physical aliases that exist in the controller. This is
0103 appropriate when the OS is responsible for managing assignment
0104 of the physical aliases.
0105 minItems: 1
0106
0107 interrupts:
0108 description: The interrupt outputs from the HW block, one per set of
0109 ports, in the order the HW manual describes them. The number of entries
0110 required varies depending on compatible value.
0111
0112 gpio-controller: true
0113
0114 "#gpio-cells":
0115 description: |
0116 Indicates how many cells are used in a consumer's GPIO specifier. In the
0117 specifier:
0118
0119 - The first cell is the pin number.
0120 See <dt-bindings/gpio/tegra186-gpio.h>.
0121 - The second cell contains flags:
0122 - Bit 0 specifies polarity
0123 - 0: Active-high (normal).
0124 - 1: Active-low (inverted).
0125 const: 2
0126
0127 interrupt-controller: true
0128
0129 "#interrupt-cells":
0130 description: |
0131 Indicates how many cells are used in a consumer's interrupt specifier.
0132 In the specifier:
0133
0134 - The first cell is the GPIO number.
0135 See <dt-bindings/gpio/tegra186-gpio.h>.
0136 - The second cell is contains flags:
0137 - Bits [3:0] indicate trigger type and level:
0138 - 1: Low-to-high edge triggered.
0139 - 2: High-to-low edge triggered.
0140 - 4: Active high level-sensitive.
0141 - 8: Active low level-sensitive.
0142
0143 Valid combinations are 1, 2, 3, 4, 8.
0144 const: 2
0145
0146 allOf:
0147 - if:
0148 properties:
0149 compatible:
0150 contains:
0151 enum:
0152 - nvidia,tegra186-gpio
0153 - nvidia,tegra194-gpio
0154 - nvidia,tegra234-gpio
0155 then:
0156 properties:
0157 interrupts:
0158 minItems: 6
0159 maxItems: 48
0160
0161 - if:
0162 properties:
0163 compatible:
0164 contains:
0165 enum:
0166 - nvidia,tegra186-gpio-aon
0167 - nvidia,tegra194-gpio-aon
0168 - nvidia,tegra234-gpio-aon
0169 then:
0170 properties:
0171 interrupts:
0172 minItems: 1
0173 maxItems: 4
0174
0175 required:
0176 - compatible
0177 - reg
0178 - reg-names
0179 - interrupts
0180
0181 additionalProperties: false
0182
0183 examples:
0184 - |
0185 #include <dt-bindings/interrupt-controller/irq.h>
0186
0187 gpio@2200000 {
0188 compatible = "nvidia,tegra186-gpio";
0189 reg-names = "security", "gpio";
0190 reg = <0x2200000 0x10000>,
0191 <0x2210000 0x10000>;
0192 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>,
0193 <0 50 IRQ_TYPE_LEVEL_HIGH>,
0194 <0 53 IRQ_TYPE_LEVEL_HIGH>,
0195 <0 56 IRQ_TYPE_LEVEL_HIGH>,
0196 <0 59 IRQ_TYPE_LEVEL_HIGH>,
0197 <0 180 IRQ_TYPE_LEVEL_HIGH>;
0198 gpio-controller;
0199 #gpio-cells = <2>;
0200 interrupt-controller;
0201 #interrupt-cells = <2>;
0202 };
0203
0204 gpio@c2f0000 {
0205 compatible = "nvidia,tegra186-gpio-aon";
0206 reg-names = "security", "gpio";
0207 reg = <0xc2f0000 0x1000>,
0208 <0xc2f1000 0x1000>;
0209 interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
0210 gpio-controller;
0211 #gpio-cells = <2>;
0212 interrupt-controller;
0213 #interrupt-cells = <2>;
0214 };
