0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/gpio/mediatek,mt7621-gpio.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Mediatek MT7621 SoC GPIO controller
0008
0009 maintainers:
0010 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
0011
0012 description: |
0013 The IP core used inside these SoCs has 3 banks of 32 GPIOs each.
0014 The registers of all the banks are interwoven inside one single IO range.
0015 We load one GPIO controller instance per bank. Also the GPIO controller can receive
0016 interrupts on any of the GPIOs, either edge or level. It then interrupts the CPU
0017 using GIC INT12.
0018
0019 properties:
0020 $nodename:
0021 pattern: "^gpio@[0-9a-f]+$"
0022
0023 compatible:
0024 const: mediatek,mt7621-gpio
0025
0026 reg:
0027 maxItems: 1
0028
0029 "#gpio-cells":
0030 const: 2
0031
0032 gpio-controller: true
0033 gpio-ranges: true
0034
0035 interrupt-controller: true
0036
0037 "#interrupt-cells":
0038 const: 2
0039
0040 interrupts:
0041 maxItems: 1
0042
0043 required:
0044 - compatible
0045 - reg
0046 - "#gpio-cells"
0047 - gpio-controller
0048 - gpio-ranges
0049 - interrupt-controller
0050 - "#interrupt-cells"
0051 - interrupts
0052
0053 additionalProperties: false
0054
0055 examples:
0056 - |
0057 #include <dt-bindings/gpio/gpio.h>
0058 #include <dt-bindings/interrupt-controller/mips-gic.h>
0059
0060 gpio@600 {
0061 compatible = "mediatek,mt7621-gpio";
0062 reg = <0x600 0x100>;
0063 #gpio-cells = <2>;
0064 gpio-controller;
0065 gpio-ranges = <&pinctrl 0 0 95>;
0066 interrupt-controller;
0067 #interrupt-cells = <2>;
0068 interrupt-parent = <&gic>;
0069 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
0070 };
0071
0072 ...
