0001 Specifying GPIO information for devices
0002 =======================================
0003
0004 1) gpios property
0005 -----------------
0006
0007 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
0008 of this GPIO for the device. While a non-existent <name> is considered valid
0009 for compatibility reasons (resolving to the "gpios" property), it is not allowed
0010 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
0011 bindings use it, but are only supported for compatibility reasons and should not
0012 be used for newer bindings since it has been deprecated.
0013
0014 GPIO properties can contain one or more GPIO phandles, but only in exceptional
0015 cases should they contain more than one. If your device uses several GPIOs with
0016 distinct functions, reference each of them under its own property, giving it a
0017 meaningful name. The only case where an array of GPIOs is accepted is when
0018 several GPIOs serve the same function (e.g. a parallel data line).
0019
0020 The exact purpose of each gpios property must be documented in the device tree
0021 binding of the device.
0022
0023 The following example could be used to describe GPIO pins used as device enable
0024 and bit-banged data signals:
0025
0026 gpio1: gpio1 {
0027 gpio-controller;
0028 #gpio-cells = <2>;
0029 };
0030 [...]
0031
0032 data-gpios = <&gpio1 12 0>,
0033 <&gpio1 13 0>,
0034 <&gpio1 14 0>,
0035 <&gpio1 15 0>;
0036
0037 In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is
0038 a local offset to the GPIO line and the second cell represent consumer flags,
0039 such as if the consumer desire the line to be active low (inverted) or open
0040 drain. This is the recommended practice.
0041
0042 The exact meaning of each specifier cell is controller specific, and must be
0043 documented in the device tree binding for the device, but it is strongly
0044 recommended to use the two-cell approach.
0045
0046 Most controllers are specifying a generic flag bitfield in the last cell, so
0047 for these, use the macros defined in
0048 include/dt-bindings/gpio/gpio.h whenever possible:
0049
0050 Example of a node using GPIOs:
0051
0052 node {
0053 enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>;
0054 };
0055
0056 GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes
0057 GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
0058
0059 Optional standard bitfield specifiers for the last cell:
0060
0061 - Bit 0: 0 means active high, 1 means active low
0062 - Bit 1: 0 mean push-pull wiring, see:
0063 https://en.wikipedia.org/wiki/Push-pull_output
0064 1 means single-ended wiring, see:
0065 https://en.wikipedia.org/wiki/Single-ended_triode
0066 - Bit 2: 0 means open-source, 1 means open drain, see:
0067 https://en.wikipedia.org/wiki/Open_collector
0068 - Bit 3: 0 means the output should be maintained during sleep/low-power mode
0069 1 means the output state can be lost during sleep/low-power mode
0070 - Bit 4: 0 means no pull-up resistor should be enabled
0071 1 means a pull-up resistor should be enabled
0072 This setting only applies to hardware with a simple on/off
0073 control for pull-up configuration. If the hardware has more
0074 elaborate pull-up configuration, it should be represented
0075 using a pin control binding.
0076 - Bit 5: 0 means no pull-down resistor should be enabled
0077 1 means a pull-down resistor should be enabled
0078 This setting only applies to hardware with a simple on/off
0079 control for pull-down configuration. If the hardware has more
0080 elaborate pull-down configuration, it should be represented
0081 using a pin control binding.
0082
0083 1.1) GPIO specifier best practices
0084 ----------------------------------
0085
0086 A gpio-specifier should contain a flag indicating the GPIO polarity; active-
0087 high or active-low. If it does, the following best practices should be
0088 followed:
0089
0090 The gpio-specifier's polarity flag should represent the physical level at the
0091 GPIO controller that achieves (or represents, for inputs) a logically asserted
0092 value at the device. The exact definition of logically asserted should be
0093 defined by the binding for the device. If the board inverts the signal between
0094 the GPIO controller and the device, then the gpio-specifier will represent the
0095 opposite physical level than the signal at the device's pin.
0096
0097 When the device's signal polarity is configurable, the binding for the
0098 device must either:
0099
0100 a) Define a single static polarity for the signal, with the expectation that
0101 any software using that binding would statically program the device to use
0102 that signal polarity.
0103
0104 The static choice of polarity may be either:
0105
0106 a1) (Preferred) Dictated by a binding-specific DT property.
0107
0108 or:
0109
0110 a2) Defined statically by the DT binding itself.
0111
0112 In particular, the polarity cannot be derived from the gpio-specifier, since
0113 that would prevent the DT from separately representing the two orthogonal
0114 concepts of configurable signal polarity in the device, and possible board-
0115 level signal inversion.
0116
0117 or:
0118
0119 b) Pick a single option for device signal polarity, and document this choice
0120 in the binding. The gpio-specifier should represent the polarity of the signal
0121 (at the GPIO controller) assuming that the device is configured for this
0122 particular signal polarity choice. If software chooses to program the device
0123 to generate or receive a signal of the opposite polarity, software will be
0124 responsible for correctly interpreting (inverting) the GPIO signal at the GPIO
0125 controller.
0126
0127 2) gpio-controller nodes
0128 ------------------------
0129
0130 Every GPIO controller node must contain both an empty "gpio-controller"
0131 property, and a #gpio-cells integer property, which indicates the number of
0132 cells in a gpio-specifier.
0133
0134 Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an
0135 instance of a hardware IP core on a silicon die, usually exposed to the
0136 programmer as a coherent range of I/O addresses. Usually each such bank is
0137 exposed in the device tree as an individual gpio-controller node, reflecting
0138 the fact that the hardware was synthesized by reusing the same IP block a
0139 few times over.
0140
0141 Optionally, a GPIO controller may have a "ngpios" property. This property
0142 indicates the number of in-use slots of available slots for GPIOs. The
0143 typical example is something like this: the hardware register is 32 bits
0144 wide, but only 18 of the bits have a physical counterpart. The driver is
0145 generally written so that all 32 bits can be used, but the IP block is reused
0146 in a lot of designs, some using all 32 bits, some using 18 and some using
0147 12. In this case, setting "ngpios = <18>;" informs the driver that only the
0148 first 18 GPIOs, at local offset 0 .. 17, are in use.
0149
0150 If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an
0151 additional set of tuples is needed to specify which GPIOs are unusable, with
0152 the gpio-reserved-ranges binding. This property indicates the start and size
0153 of the GPIOs that can't be used.
0154
0155 Optionally, a GPIO controller may have a "gpio-line-names" property. This is
0156 an array of strings defining the names of the GPIO lines going out of the
0157 GPIO controller. This name should be the most meaningful producer name
0158 for the system, such as a rail name indicating the usage. Package names
0159 such as pin name are discouraged: such lines have opaque names (since they
0160 are by definition generic purpose) and such names are usually not very
0161 helpful. For example "MMC-CD", "Red LED Vdd" and "ethernet reset" are
0162 reasonable line names as they describe what the line is used for. "GPIO0"
0163 is not a good name to give to a GPIO line. Placeholders are discouraged:
0164 rather use the "" (blank string) if the use of the GPIO line is undefined
0165 in your design. The names are assigned starting from line offset 0 from
0166 left to right from the passed array. An incomplete array (where the number
0167 of passed named are less than ngpios) will still be used up until the last
0168 provided valid line index.
0169
0170 Example:
0171
0172 gpio-controller@00000000 {
0173 compatible = "foo";
0174 reg = <0x00000000 0x1000>;
0175 gpio-controller;
0176 #gpio-cells = <2>;
0177 ngpios = <18>;
0178 gpio-reserved-ranges = <0 4>, <12 2>;
0179 gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R",
0180 "LED G", "LED B", "Col A", "Col B", "Col C", "Col D",
0181 "Row A", "Row B", "Row C", "Row D", "NMI button",
0182 "poweroff", "reset";
0183 }
0184
0185 The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
0186 providing automatic GPIO request and configuration as part of the
0187 gpio-controller's driver probe function.
0188
0189 Each GPIO hog definition is represented as a child node of the GPIO controller.
0190 Required properties:
0191 - gpio-hog: A property specifying that this child node represents a GPIO hog.
0192 - gpios: Store the GPIO information (id, flags, ...) for each GPIO to
0193 affect. Shall contain an integer multiple of the number of cells
0194 specified in its parent node (GPIO controller node).
0195 Only one of the following properties scanned in the order shown below.
0196 This means that when multiple properties are present they will be searched
0197 in the order presented below and the first match is taken as the intended
0198 configuration.
0199 - input: A property specifying to set the GPIO direction as input.
0200 - output-low A property specifying to set the GPIO direction as output with
0201 the value low.
0202 - output-high A property specifying to set the GPIO direction as output with
0203 the value high.
0204
0205 Optional properties:
0206 - line-name: The GPIO label name. If not present the node name is used.
0207
0208 Example of two SOC GPIO banks defined as gpio-controller nodes:
0209
0210 qe_pio_a: gpio-controller@1400 {
0211 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
0212 reg = <0x1400 0x18>;
0213 gpio-controller;
0214 #gpio-cells = <2>;
0215
0216 line_b-hog {
0217 gpio-hog;
0218 gpios = <6 0>;
0219 output-low;
0220 line-name = "foo-bar-gpio";
0221 };
0222 };
0223
0224 qe_pio_e: gpio-controller@1460 {
0225 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
0226 reg = <0x1460 0x18>;
0227 gpio-controller;
0228 #gpio-cells = <2>;
0229 };
0230
0231 2.1) gpio- and pin-controller interaction
0232 -----------------------------------------
0233
0234 Some or all of the GPIOs provided by a GPIO controller may be routed to pins
0235 on the package via a pin controller. This allows muxing those pins between
0236 GPIO and other functions. It is a fairly common practice among silicon
0237 engineers.
0238
0239 2.2) Ordinary (numerical) GPIO ranges
0240 -------------------------------------
0241
0242 It is useful to represent which GPIOs correspond to which pins on which pin
0243 controllers. The gpio-ranges property described below represents this with
0244 a discrete set of ranges mapping pins from the pin controller local number space
0245 to pins in the GPIO controller local number space.
0246
0247 The format is: <[pin controller phandle], [GPIO controller offset],
0248 [pin controller offset], [number of pins]>;
0249
0250 The GPIO controller offset pertains to the GPIO controller node containing the
0251 range definition.
0252
0253 The pin controller node referenced by the phandle must conform to the bindings
0254 described in pinctrl/pinctrl-bindings.txt.
0255
0256 Each offset runs from 0 to N. It is perfectly fine to pile any number of
0257 ranges with just one pin-to-GPIO line mapping if the ranges are concocted, but
0258 in practice these ranges are often lumped in discrete sets.
0259
0260 Example:
0261
0262 gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>;
0263
0264 This means:
0265 - pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9 and
0266 - pins 50..69 on pin controller "bar" is mapped to GPIO line 10..29
0267
0268
0269 Verbose example:
0270
0271 qe_pio_e: gpio-controller@1460 {
0272 #gpio-cells = <2>;
0273 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
0274 reg = <0x1460 0x18>;
0275 gpio-controller;
0276 gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
0277 };
0278
0279 Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
0280 pinctrl1's pins 20..29, and GPIOs 10..29 routed to pin controller pinctrl2's
0281 pins 50..69.
0282
0283
0284 2.3) GPIO ranges from named pin groups
0285 --------------------------------------
0286
0287 It is also possible to use pin groups for gpio ranges when pin groups are the
0288 easiest and most convenient mapping.
0289
0290 Both both <pinctrl-base> and <count> must set to 0 when using named pin groups
0291 names.
0292
0293 The property gpio-ranges-group-names must contain exactly one string for each
0294 range.
0295
0296 Elements of gpio-ranges-group-names must contain the name of a pin group
0297 defined in the respective pin controller. The number of pins/GPIO lines in the
0298 range is the number of pins in that pin group. The number of pins of that
0299 group is defined int the implementation and not in the device tree.
0300
0301 If numerical and named pin groups are mixed, the string corresponding to a
0302 numerical pin range in gpio-ranges-group-names must be empty.
0303
0304 Example:
0305
0306 gpio_pio_i: gpio-controller@14b0 {
0307 #gpio-cells = <2>;
0308 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
0309 reg = <0x1480 0x18>;
0310 gpio-controller;
0311 gpio-ranges = <&pinctrl1 0 20 10>,
0312 <&pinctrl2 10 0 0>,
0313 <&pinctrl1 15 0 10>,
0314 <&pinctrl2 25 0 0>;
0315 gpio-ranges-group-names = "",
0316 "foo",
0317 "",
0318 "bar";
0319 };
0320
0321 Here, three GPIO ranges are defined referring to two pin controllers.
0322
0323 pinctrl1 GPIO ranges are defined using pin numbers whereas the GPIO ranges
0324 in pinctrl2 are defined using the pin groups named "foo" and "bar".
0325
0326 Previous versions of this binding required all pin controller nodes that
0327 were referenced by any gpio-ranges property to contain a property named
0328 #gpio-range-cells with value <3>. This requirement is now deprecated.
0329 However, that property may still exist in older device trees for
0330 compatibility reasons, and would still be required even in new device
0331 trees that need to be compatible with older software.
