0001 Xilinx plb/axi GPIO controller
0002
0003 Dual channel GPIO controller with configurable number of pins
0004 (from 1 to 32 per channel). Every pin can be configured as
0005 input/output/tristate. Both channels share the same global IRQ but
0006 local interrupts can be enabled on channel basis.
0007
0008 Required properties:
0009 - compatible : Should be "xlnx,xps-gpio-1.00.a"
0010 - reg : Address and length of the register set for the device
0011 - #gpio-cells : Should be two. The first cell is the pin number and the
0012 second cell is used to specify optional parameters (currently unused).
0013 - gpio-controller : Marks the device node as a GPIO controller.
0014
0015 Optional properties:
0016 - clocks : Input clock specifier. Refer to common clock bindings.
0017 - interrupts : Interrupt mapping for GPIO IRQ.
0018 - xlnx,all-inputs : if n-th bit is setup, GPIO-n is input
0019 - xlnx,dout-default : if n-th bit is 1, GPIO-n default value is 1
0020 - xlnx,gpio-width : gpio width
0021 - xlnx,tri-default : if n-th bit is 1, GPIO-n is in tristate mode
0022 - xlnx,is-dual : if 1, controller also uses the second channel
0023 - xlnx,all-inputs-2 : as above but for the second channel
0024 - xlnx,dout-default-2 : as above but the second channel
0025 - xlnx,gpio2-width : as above but for the second channel
0026 - xlnx,tri-default-2 : as above but for the second channel
0027
0028
0029 Example:
0030 gpio: gpio@40000000 {
0031 #gpio-cells = <2>;
0032 compatible = "xlnx,xps-gpio-1.00.a";
0033 clocks = <&clkc25>;
0034 gpio-controller ;
0035 interrupt-parent = <µblaze_0_intc>;
0036 interrupts = < 6 2 >;
0037 reg = < 0x40000000 0x10000 >;
0038 xlnx,all-inputs = <0x0>;
0039 xlnx,all-inputs-2 = <0x0>;
0040 xlnx,dout-default = <0x0>;
0041 xlnx,dout-default-2 = <0x0>;
0042 xlnx,gpio-width = <0x2>;
0043 xlnx,gpio2-width = <0x2>;
0044 xlnx,interrupt-present = <0x1>;
0045 xlnx,is-dual = <0x1>;
0046 xlnx,tri-default = <0xffffffff>;
0047 xlnx,tri-default-2 = <0xffffffff>;
0048 } ;
