0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/gpio/gpio-stp-xway.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Lantiq SoC Serial To Parallel (STP) GPIO controller
0008
0009 description: |
0010 The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
0011 peripheral controller used to drive external shift register cascades. At most
0012 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
0013 and Ethernet PHYs to drive some bytes of the cascade automatically.
0014
0015 maintainers:
0016 - John Crispin <john@phrozen.org>
0017
0018 properties:
0019 $nodename:
0020 pattern: "^gpio@[0-9a-f]+$"
0021
0022 compatible:
0023 const: lantiq,gpio-stp-xway
0024
0025 reg:
0026 maxItems: 1
0027
0028 gpio-controller: true
0029
0030 "#gpio-cells":
0031 description:
0032 The first cell is the pin number and the second cell is used to specify
0033 consumer flags.
0034 const: 2
0035
0036 lantiq,shadow:
0037 description:
0038 The default value that we shall assume as already set on the
0039 shift register cascade.
0040 $ref: /schemas/types.yaml#/definitions/uint32
0041 minimum: 0x000000
0042 maximum: 0xffffff
0043
0044 lantiq,groups:
0045 description:
0046 Set the 3 bit mask to select which of the 3 groups are enabled
0047 in the shift register cascade.
0048 $ref: /schemas/types.yaml#/definitions/uint32
0049 minimum: 0x0
0050 maximum: 0x7
0051
0052 lantiq,dsl:
0053 description:
0054 The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit
0055 property can enable this feature.
0056 $ref: /schemas/types.yaml#/definitions/uint32
0057 minimum: 0x0
0058 maximum: 0x3
0059
0060 lantiq,rising:
0061 description:
0062 Use rising instead of falling edge for the shift register.
0063 type: boolean
0064
0065 patternProperties:
0066 "^lantiq,phy[1-4]$":
0067 description:
0068 The gphy core can control 3 bits of the gpio cascade. In the xRX200 family
0069 phy[1-2] are available, in xRX330 phy[1-3] and in XRX330 phy[1-4].
0070 $ref: /schemas/types.yaml#/definitions/uint32
0071 minimum: 0x0
0072 maximum: 0x7
0073
0074 required:
0075 - compatible
0076 - reg
0077 - gpio-controller
0078 - "#gpio-cells"
0079
0080 additionalProperties: false
0081
0082 examples:
0083 - |
0084 gpio@e100bb0 {
0085 compatible = "lantiq,gpio-stp-xway";
0086 reg = <0xE100BB0 0x40>;
0087 #gpio-cells = <2>;
0088 gpio-controller;
0089
0090 pinctrl-0 = <&stp_pins>;
0091 pinctrl-names = "default";
0092
0093 lantiq,shadow = <0xffffff>;
0094 lantiq,groups = <0x7>;
0095 lantiq,dsl = <0x3>;
0096 lantiq,phy1 = <0x7>;
0097 lantiq,phy2 = <0x7>;
0098 };
0099 ...
