bindings/gpio/gpio-mvebu.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Marvell EBU GPIO controller
0008
0009 maintainers:
0010   - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0011   - Andrew Lunn <andrew@lunn.ch>
0012
0013 properties:
0014   compatible:
0015     oneOf:
0016       - enum:
0017           - marvell,armada-8k-gpio
0018           - marvell,orion-gpio
0019
0020       - items:
0021           - enum:
0022               - marvell,mv78200-gpio
0023               - marvell,armada-370-gpio
0024           - const: marvell,orion-gpio
0025
0026       - description: Deprecated binding
0027         items:
0028           - const: marvell,armadaxp-gpio
0029           - const: marvell,orion-gpio
0030         deprecated: true
0031
0032   reg:
0033     description: |
0034       Address and length of the register set for the device. Not used for
0035       marvell,armada-8k-gpio.
0036
0037       A second entry can be provided, for the PWM function using the GPIO Blink
0038       Counter on/off registers.
0039     minItems: 1
0040     maxItems: 2
0041
0042   reg-names:
0043     items:
0044       - const: gpio
0045       - const: pwm
0046     minItems: 1
0047
0048   offset:
0049     $ref: /schemas/types.yaml#/definitions/uint32
0050     description: Offset in the register map for the gpio registers (in bytes)
0051
0052   interrupts:
0053     description: |
0054       The list of interrupts that are used for all the pins managed by this
0055       GPIO bank. There can be more than one interrupt (example: 1 interrupt
0056       per 8 pins on Armada XP, which means 4 interrupts per bank of 32
0057       GPIOs).
0058     minItems: 1
0059     maxItems: 4
0060
0061   interrupt-controller: true
0062
0063   "#interrupt-cells":
0064     const: 2
0065
0066   gpio-controller: true
0067
0068   ngpios:
0069     minimum: 1
0070     maximum: 32
0071
0072   "#gpio-cells":
0073     const: 2
0074
0075   marvell,pwm-offset:
0076     $ref: /schemas/types.yaml#/definitions/uint32
0077     description: Offset in the register map for the pwm registers (in bytes)
0078
0079   "#pwm-cells":
0080     description:
0081       The first cell is the GPIO line number. The second cell is the period
0082       in nanoseconds.
0083     const: 2
0084
0085   clocks:
0086     description:
0087       Clock(s) used for PWM function.
0088     items:
0089       - description: Core clock
0090       - description: AXI bus clock
0091     minItems: 1
0092
0093   clock-names:
0094     items:
0095       - const: core
0096       - const: axi
0097     minItems: 1
0098
0099 required:
0100   - compatible
0101   - gpio-controller
0102   - ngpios
0103   - "#gpio-cells"
0104
0105 allOf:
0106   - if:
0107       properties:
0108         compatible:
0109           contains:
0110             const: marvell,armada-8k-gpio
0111     then:
0112       required:
0113         - offset
0114     else:
0115       required:
0116         - reg
0117
0118 unevaluatedProperties: true
0119
0120 examples:
0121   - |
0122     gpio@d0018100 {
0123       compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio";
0124       reg = <0xd0018100 0x40>, <0xd0018800 0x30>;
0125       ngpios = <32>;
0126       gpio-controller;
0127       #gpio-cells = <2>;
0128       interrupt-controller;
0129       #interrupt-cells = <2>;
0130       interrupts = <16>, <17>, <18>, <19>;
0131     };
0132
0133   - |
0134     gpio@18140 {
0135       compatible = "marvell,armada-370-gpio", "marvell,orion-gpio";
0136       reg = <0x18140 0x40>, <0x181c8 0x08>;
0137       reg-names = "gpio", "pwm";
0138       ngpios = <17>;
0139       gpio-controller;
0140       #gpio-cells = <2>;
0141       #pwm-cells = <2>;
0142       interrupt-controller;
0143       #interrupt-cells = <2>;
0144       interrupts = <87>, <88>, <89>;
0145       clocks = <&coreclk 0>;
0146     };