0001 Keystone 2 DSP GPIO controller bindings
0002
0003 HOST OS userland running on ARM can send interrupts to DSP cores using
0004 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
0005 This is one of the component used by the IPC mechanism used on Keystone SOCs.
0006
0007 For example TCI6638K2K SoC has 8 DSP GPIO controllers:
0008 - 8 for C66x CorePacx CPUs 0-7
0009
0010 Keystone 2 DSP GPIO controller has specific features:
0011 - each GPIO can be configured only as output pin;
0012 - setting GPIO value to 1 causes IRQ generation on target DSP core;
0013 - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
0014 pending.
0015
0016 Required Properties:
0017 - compatible: should be "ti,keystone-dsp-gpio"
0018 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
0019 access device state control registers and the offset of device's specific
0020 registers within device state control registers range.
0021 - gpio-controller: Marks the device node as a gpio controller.
0022 - #gpio-cells: Should be 2.
0023
0024 Please refer to gpio.txt in this directory for details of the common GPIO
0025 bindings used by client devices.
0026
0027 Example:
0028 dspgpio0: keystone_dsp_gpio@2620240 {
0029 compatible = "ti,keystone-dsp-gpio";
0030 ti,syscon-dev = <&devctrl 0x240>;
0031 gpio-controller;
0032 #gpio-cells = <2>;
0033 };
0034
0035 dsp0: dsp0 {
0036 compatible = "linux,rproc-user";
0037 ...
0038 kick-gpio = <&dspgpio0 27>;
0039 };
