0001 * General Purpose Input Output (GPIO) bus.
0002
0003 Properties:
0004 - compatible: "cavium,octeon-3860-gpio"
0005
0006 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
0007
0008 - reg: The base address of the GPIO unit's register bank.
0009
0010 - gpio-controller: This is a GPIO controller.
0011
0012 - #gpio-cells: Must be <2>. The first cell is the GPIO pin.
0013
0014 - interrupt-controller: The GPIO controller is also an interrupt
0015 controller, many of its pins may be configured as an interrupt
0016 source.
0017
0018 - #interrupt-cells: Must be <2>. The first cell is the GPIO pin
0019 connected to the interrupt source. The second cell is the interrupt
0020 triggering protocol and may have one of four values:
0021 1 - edge triggered on the rising edge.
0022 2 - edge triggered on the falling edge
0023 4 - level triggered active high.
0024 8 - level triggered active low.
0025
0026 - interrupts: Interrupt routing for each pin.
0027
0028 Example:
0029
0030 gpio-controller@1070000000800 {
0031 #gpio-cells = <2>;
0032 compatible = "cavium,octeon-3860-gpio";
0033 reg = <0x10700 0x00000800 0x0 0x100>;
0034 gpio-controller;
0035 /* Interrupts are specified by two parts:
0036 * 1) GPIO pin number (0..15)
0037 * 2) Triggering (1 - edge rising
0038 * 2 - edge falling
0039 * 4 - level active high
0040 * 8 - level active low)
0041 */
0042 interrupt-controller;
0043 #interrupt-cells = <2>;
0044 /* The GPIO pin connect to 16 consecutive CUI bits */
0045 interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
0046 <0 20>, <0 21>, <0 22>, <0 23>,
0047 <0 24>, <0 25>, <0 26>, <0 27>,
0048 <0 28>, <0 29>, <0 30>, <0 31>;
0049 };
