0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Broadcom STB "UPG GIO" GPIO controller
0008
0009 description: >
0010 The controller's registers are organized as sets of eight 32-bit
0011 registers with each set controlling a bank of up to 32 pins. A single
0012 interrupt is shared for all of the banks handled by the controller.
0013
0014 maintainers:
0015 - Doug Berger <opendmb@gmail.com>
0016 - Florian Fainelli <f.fainelli@gmail.com>
0017
0018 properties:
0019 compatible:
0020 items:
0021 - enum:
0022 - brcm,bcm7445-gpio
0023 - const: brcm,brcmstb-gpio
0024
0025 reg:
0026 maxItems: 1
0027 description: >
0028 Define the base and range of the I/O address space containing
0029 the brcmstb GPIO controller registers
0030
0031 "#gpio-cells":
0032 const: 2
0033 description: >
0034 The first cell is the pin number (within the controller's
0035 pin space), and the second is used for the following:
0036 bit[0]: polarity (0 for active-high, 1 for active-low)
0037
0038 gpio-controller: true
0039
0040 brcm,gpio-bank-widths:
0041 $ref: /schemas/types.yaml#/definitions/uint32-array
0042 description: >
0043 Number of GPIO lines for each bank. Number of elements must
0044 correspond to number of banks suggested by the 'reg' property.
0045
0046 interrupts:
0047 maxItems: 1
0048 description: >
0049 The interrupt shared by all GPIO lines for this controller.
0050
0051 "#interrupt-cells":
0052 const: 2
0053 description: |
0054 The first cell is the GPIO number, the second should specify
0055 flags. The following subset of flags is supported:
0056 - bits[3:0] trigger type and level flags
0057 1 = low-to-high edge triggered
0058 2 = high-to-low edge triggered
0059 4 = active high level-sensitive
0060 8 = active low level-sensitive
0061 Valid combinations are 1, 2, 3, 4, 8.
0062
0063 interrupt-controller: true
0064
0065 wakeup-source:
0066 type: boolean
0067 description: >
0068 GPIOs for this controller can be used as a wakeup source
0069
0070 required:
0071 - compatible
0072 - reg
0073 - gpio-controller
0074 - "#gpio-cells"
0075 - "brcm,gpio-bank-widths"
0076
0077 additionalProperties: false
0078
0079 examples:
0080 - |
0081 upg_gio: gpio@f040a700 {
0082 #gpio-cells = <2>;
0083 #interrupt-cells = <2>;
0084 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
0085 gpio-controller;
0086 interrupt-controller;
0087 reg = <0xf040a700 0x80>;
0088 interrupt-parent = <&irq0_intc>;
0089 interrupts = <0x6>;
0090 brcm,gpio-bank-widths = <32 32 32 24>;
0091 };
0092
0093 upg_gio_aon: gpio@f04172c0 {
0094 #gpio-cells = <2>;
0095 #interrupt-cells = <2>;
0096 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
0097 gpio-controller;
0098 interrupt-controller;
0099 reg = <0xf04172c0 0x40>;
0100 interrupt-parent = <&irq0_aon_intc>;
0101 interrupts = <0x6>;
0102 wakeup-source;
0103 brcm,gpio-bank-widths = <18 4>;
0104 };
