0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager Device Tree Bindings
0008
0009 maintainers:
0010 - Nava kishore Manne <navam@xilinx.com>
0011
0012 description: |
0013 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
0014 The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
0015 configure the Programmable Logic (PL). The configuration uses the
0016 firmware interface.
0017
0018 properties:
0019 compatible:
0020 const: xlnx,zynqmp-pcap-fpga
0021
0022 required:
0023 - compatible
0024
0025 additionalProperties: false
0026
0027 examples:
0028 - |
0029 firmware {
0030 zynqmp_firmware: zynqmp-firmware {
0031 zynqmp_pcap: pcap {
0032 compatible = "xlnx,zynqmp-pcap-fpga";
0033 };
0034 };
0035 };
0036 ...
