bindings/fpga/xilinx-zynq-fpga-mgr.yaml

0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Xilinx Zynq FPGA Manager Device Tree Bindings
0008
0009 maintainers:
0010   - Michal Simek <michal.simek@xilinx.com>
0011
0012 properties:
0013   compatible:
0014     const: xlnx,zynq-devcfg-1.0
0015
0016   reg:
0017     maxItems: 1
0018
0019   interrupts:
0020     maxItems: 1
0021
0022   clocks:
0023     maxItems: 1
0024
0025   clock-names:
0026     items:
0027       - const: ref_clk
0028
0029   syscon:
0030     $ref: /schemas/types.yaml#/definitions/phandle
0031     description:
0032       Phandle to syscon block which provide access to SLCR registers
0033
0034 required:
0035   - compatible
0036   - reg
0037   - clocks
0038   - clock-names
0039   - syscon
0040
0041 additionalProperties: false
0042
0043 examples:
0044   - |
0045     devcfg: devcfg@f8007000 {
0046       compatible = "xlnx,zynq-devcfg-1.0";
0047       reg = <0xf8007000 0x100>;
0048       interrupts = <0 8 4>;
0049       clocks = <&clkc 12>;
0050       clock-names = "ref_clk";
0051       syscon = <&slcr>;
0052     };