0001 Xilinx Slave Serial SPI FPGA Manager
0002
0003 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
0004 bitstream over what is referred to as "slave serial" interface.
0005 The slave serial link is not technically SPI, and might require extra
0006 circuits in order to play nicely with other SPI slaves on the same bus.
0007
0008 See:
0009 - https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
0010 - https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
0011 - https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
0012
0013 Required properties:
0014 - compatible: should contain "xlnx,fpga-slave-serial"
0015 - reg: spi chip select of the FPGA
0016 - prog_b-gpios: config pin (referred to as PROGRAM_B in the manual)
0017 - done-gpios: config status pin (referred to as DONE in the manual)
0018
0019 Optional properties:
0020 - init-b-gpios: initialization status and configuration error pin
0021 (referred to as INIT_B in the manual)
0022
0023 Example for full FPGA configuration:
0024
0025 fpga-region0 {
0026 compatible = "fpga-region";
0027 fpga-mgr = <&fpga_mgr_spi>;
0028 #address-cells = <0x1>;
0029 #size-cells = <0x1>;
0030 };
0031
0032 spi1: spi@10680 {
0033 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
0034 pinctrl-0 = <&spi0_pins>;
0035 pinctrl-names = "default";
0036 #address-cells = <1>;
0037 #size-cells = <0>;
0038 cell-index = <1>;
0039 interrupts = <92>;
0040 clocks = <&coreclk 0>;
0041
0042 fpga_mgr_spi: fpga-mgr@0 {
0043 compatible = "xlnx,fpga-slave-serial";
0044 spi-max-frequency = <60000000>;
0045 spi-cpha;
0046 reg = <0>;
0047 prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
0048 init-b-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
0049 done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
0050 };
0051 };
