bindings/fpga/altera-passive-serial.txt

0001 Altera Passive Serial SPI FPGA Manager
0002
0003 Altera FPGAs support a method of loading the bitstream over what is
0004 referred to as "passive serial".
0005 The passive serial link is not technically SPI, and might require extra
0006 circuits in order to play nicely with other SPI slaves on the same bus.
0007
0008 See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
0009
0010 Required properties:
0011 - compatible: Must be one of the following:
0012         "altr,fpga-passive-serial",
0013         "altr,fpga-arria10-passive-serial"
0014 - reg: SPI chip select of the FPGA
0015 - nconfig-gpios: config pin (referred to as nCONFIG in the manual)
0016 - nstat-gpios: status pin (referred to as nSTATUS in the manual)
0017
0018 Optional properties:
0019 - confd-gpios: confd pin (referred to as CONF_DONE in the manual)
0020
0021 Example:
0022         fpga: fpga@0 {
0023                 compatible = "altr,fpga-passive-serial";
0024                 spi-max-frequency = <20000000>;
0025                 reg = <0>;
0026                 nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
0027                 nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
0028                 confd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
0029         };